mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 23:40:54 +07:00
c284d9fa48
This patch fix a bug in the register indexing for GPIOs numbers > 31 to get the relevant hardware registers of tnetv107x to control the GPIOs. In the structure tnetv107x_gpio_regs: struct tnetv107x_gpio_regs { u32 idver; u32 data_in[3]; u32 data_out[3]; u32 direction[3]; u32 enable[3]; }; The GPIO hardware register addresses of tnetv107x are stored. The chip implements 3 registers of each entity to serve 96 GPIOs, each register provides a subset of 32 GPIOs. The driver provides these macros: gpio_reg_set_bit, gpio_reg_get_bit and gpio_reg_clear_bit. The bug implied the use of macros to access the relevant hardware register e.g. the driver code used the macro like this: 'gpio_reg_clear_bit(®->data_out, gpio)' But it has to be used like this: 'gpio_reg_clear_bit(reg->data_out, gpio)'. The different results are shown here: - ®->data_out + 1 (it will add the full array size of data_out i.e. 12 bytes) - reg->data_out + 1 (it will increment only the size of data_out i.e. only 4 bytes) Acked-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Hirosh Dabui <hirosh.dabui@snom.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
206 lines
5.3 KiB
C
206 lines
5.3 KiB
C
/*
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* Texas Instruments TNETV107X GPIO Controller
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*
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* Copyright (C) 2010 Texas Instruments
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/gpio.h>
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#include <mach/common.h>
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#include <mach/tnetv107x.h>
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struct tnetv107x_gpio_regs {
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u32 idver;
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u32 data_in[3];
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u32 data_out[3];
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u32 direction[3];
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u32 enable[3];
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};
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#define gpio_reg_index(gpio) ((gpio) >> 5)
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#define gpio_reg_bit(gpio) BIT((gpio) & 0x1f)
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#define gpio_reg_rmw(reg, mask, val) \
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__raw_writel((__raw_readl(reg) & ~(mask)) | (val), (reg))
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#define gpio_reg_set_bit(reg, gpio) \
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gpio_reg_rmw((reg) + gpio_reg_index(gpio), 0, gpio_reg_bit(gpio))
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#define gpio_reg_clear_bit(reg, gpio) \
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gpio_reg_rmw((reg) + gpio_reg_index(gpio), gpio_reg_bit(gpio), 0)
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#define gpio_reg_get_bit(reg, gpio) \
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(__raw_readl((reg) + gpio_reg_index(gpio)) & gpio_reg_bit(gpio))
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#define chip2controller(chip) \
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container_of(chip, struct davinci_gpio_controller, chip)
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#define TNETV107X_GPIO_CTLRS DIV_ROUND_UP(TNETV107X_N_GPIO, 32)
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static struct davinci_gpio_controller chips[TNETV107X_GPIO_CTLRS];
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static int tnetv107x_gpio_request(struct gpio_chip *chip, unsigned offset)
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{
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struct davinci_gpio_controller *ctlr = chip2controller(chip);
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struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
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unsigned gpio = chip->base + offset;
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unsigned long flags;
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spin_lock_irqsave(&ctlr->lock, flags);
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gpio_reg_set_bit(regs->enable, gpio);
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spin_unlock_irqrestore(&ctlr->lock, flags);
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return 0;
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}
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static void tnetv107x_gpio_free(struct gpio_chip *chip, unsigned offset)
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{
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struct davinci_gpio_controller *ctlr = chip2controller(chip);
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struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
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unsigned gpio = chip->base + offset;
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unsigned long flags;
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spin_lock_irqsave(&ctlr->lock, flags);
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gpio_reg_clear_bit(regs->enable, gpio);
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spin_unlock_irqrestore(&ctlr->lock, flags);
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}
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static int tnetv107x_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
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{
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struct davinci_gpio_controller *ctlr = chip2controller(chip);
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struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
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unsigned gpio = chip->base + offset;
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unsigned long flags;
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spin_lock_irqsave(&ctlr->lock, flags);
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gpio_reg_set_bit(regs->direction, gpio);
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spin_unlock_irqrestore(&ctlr->lock, flags);
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return 0;
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}
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static int tnetv107x_gpio_dir_out(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct davinci_gpio_controller *ctlr = chip2controller(chip);
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struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
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unsigned gpio = chip->base + offset;
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unsigned long flags;
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spin_lock_irqsave(&ctlr->lock, flags);
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if (value)
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gpio_reg_set_bit(regs->data_out, gpio);
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else
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gpio_reg_clear_bit(regs->data_out, gpio);
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gpio_reg_clear_bit(regs->direction, gpio);
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spin_unlock_irqrestore(&ctlr->lock, flags);
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return 0;
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}
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static int tnetv107x_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct davinci_gpio_controller *ctlr = chip2controller(chip);
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struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
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unsigned gpio = chip->base + offset;
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int ret;
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ret = gpio_reg_get_bit(regs->data_in, gpio);
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return ret ? 1 : 0;
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}
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static void tnetv107x_gpio_set(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct davinci_gpio_controller *ctlr = chip2controller(chip);
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struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
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unsigned gpio = chip->base + offset;
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unsigned long flags;
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spin_lock_irqsave(&ctlr->lock, flags);
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if (value)
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gpio_reg_set_bit(regs->data_out, gpio);
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else
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gpio_reg_clear_bit(regs->data_out, gpio);
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spin_unlock_irqrestore(&ctlr->lock, flags);
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}
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static int __init tnetv107x_gpio_setup(void)
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{
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int i, base;
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unsigned ngpio;
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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struct tnetv107x_gpio_regs *regs;
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struct davinci_gpio_controller *ctlr;
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if (soc_info->gpio_type != GPIO_TYPE_TNETV107X)
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return 0;
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ngpio = soc_info->gpio_num;
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if (ngpio == 0) {
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pr_err("GPIO setup: how many GPIOs?\n");
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return -EINVAL;
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}
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if (WARN_ON(TNETV107X_N_GPIO < ngpio))
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ngpio = TNETV107X_N_GPIO;
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regs = ioremap(soc_info->gpio_base, SZ_4K);
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if (WARN_ON(!regs))
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return -EINVAL;
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for (i = 0, base = 0; base < ngpio; i++, base += 32) {
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ctlr = &chips[i];
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ctlr->chip.label = "tnetv107x";
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ctlr->chip.can_sleep = 0;
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ctlr->chip.base = base;
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ctlr->chip.ngpio = ngpio - base;
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if (ctlr->chip.ngpio > 32)
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ctlr->chip.ngpio = 32;
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ctlr->chip.request = tnetv107x_gpio_request;
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ctlr->chip.free = tnetv107x_gpio_free;
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ctlr->chip.direction_input = tnetv107x_gpio_dir_in;
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ctlr->chip.get = tnetv107x_gpio_get;
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ctlr->chip.direction_output = tnetv107x_gpio_dir_out;
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ctlr->chip.set = tnetv107x_gpio_set;
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spin_lock_init(&ctlr->lock);
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ctlr->regs = regs;
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ctlr->set_data = ®s->data_out[i];
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ctlr->clr_data = ®s->data_out[i];
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ctlr->in_data = ®s->data_in[i];
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gpiochip_add(&ctlr->chip);
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}
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soc_info->gpio_ctlrs = chips;
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soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
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return 0;
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}
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pure_initcall(tnetv107x_gpio_setup);
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