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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b2ae318acd
First of all GMCH can be considered a feature by itself
since it is a chip present in some platforms that connects
the IA processor to memory and other components in PC.
Also with the introduction of display block at device info,
we got a redundant definition:
.display.has_gmch_display = 1,
So, let's clean up things a bit and use the standardized
way of has_feature on displays side.
No functional change and no manual interaction to generate
this patch.
It is only:
sed -si -e 's/has_gmch_display/has_gmch/g' \
-e 's/HAS_GMCH_DISPLAY/HAS_GMCH/g' drivers/gpu/drm/i915/*{c,h}
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190204222538.15842-1-rodrigo.vivi@intel.com
149 lines
4.6 KiB
C
149 lines
4.6 KiB
C
/*
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*
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* Copyright 2008 (c) Intel Corporation
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* Jesse Barnes <jbarnes@virtuousgeek.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <drm/i915_drm.h>
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#include "intel_drv.h"
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#include "i915_reg.h"
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static void i915_save_display(struct drm_i915_private *dev_priv)
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{
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/* Display arbitration control */
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if (INTEL_GEN(dev_priv) <= 4)
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dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
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/* save FBC interval */
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if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
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dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
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}
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static void i915_restore_display(struct drm_i915_private *dev_priv)
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{
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/* Display arbitration */
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if (INTEL_GEN(dev_priv) <= 4)
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I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
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/* only restore FBC info on the platform that supports FBC*/
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intel_fbc_global_disable(dev_priv);
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/* restore FBC interval */
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if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
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I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
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i915_redisable_vga(dev_priv);
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}
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int i915_save_state(struct drm_i915_private *dev_priv)
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{
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struct pci_dev *pdev = dev_priv->drm.pdev;
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int i;
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mutex_lock(&dev_priv->drm.struct_mutex);
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i915_save_display(dev_priv);
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if (IS_GEN(dev_priv, 4))
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pci_read_config_word(pdev, GCDGMBUS,
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&dev_priv->regfile.saveGCDGMBUS);
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/* Cache mode state */
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if (INTEL_GEN(dev_priv) < 7)
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dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
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/* Memory Arbitration state */
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dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
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/* Scratch space */
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if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
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for (i = 0; i < 7; i++) {
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dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
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dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
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}
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for (i = 0; i < 3; i++)
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dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
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} else if (IS_GEN(dev_priv, 2)) {
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for (i = 0; i < 7; i++)
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dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
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} else if (HAS_GMCH(dev_priv)) {
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for (i = 0; i < 16; i++) {
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dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
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dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
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}
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for (i = 0; i < 3; i++)
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dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
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}
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mutex_unlock(&dev_priv->drm.struct_mutex);
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return 0;
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}
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int i915_restore_state(struct drm_i915_private *dev_priv)
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{
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struct pci_dev *pdev = dev_priv->drm.pdev;
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int i;
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mutex_lock(&dev_priv->drm.struct_mutex);
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if (IS_GEN(dev_priv, 4))
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pci_write_config_word(pdev, GCDGMBUS,
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dev_priv->regfile.saveGCDGMBUS);
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i915_restore_display(dev_priv);
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/* Cache mode state */
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if (INTEL_GEN(dev_priv) < 7)
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I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
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0xffff0000);
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/* Memory arbitration state */
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I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
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/* Scratch space */
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if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
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for (i = 0; i < 7; i++) {
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I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
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I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
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}
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for (i = 0; i < 3; i++)
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I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
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} else if (IS_GEN(dev_priv, 2)) {
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for (i = 0; i < 7; i++)
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I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
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} else if (HAS_GMCH(dev_priv)) {
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for (i = 0; i < 16; i++) {
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I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
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I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
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}
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for (i = 0; i < 3; i++)
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I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
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}
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mutex_unlock(&dev_priv->drm.struct_mutex);
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intel_i2c_reset(dev_priv);
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return 0;
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}
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