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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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47f38501f1
Cleanup the kernel context handling. v2: rebased Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> (v1)
146 lines
4.2 KiB
C
146 lines
4.2 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*
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*/
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#include <linux/kthread.h>
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#include <linux/wait.h>
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#include <linux/sched.h>
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#include <drm/drmP.h>
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#include "amdgpu.h"
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static int amdgpu_sched_prepare_job(struct amd_gpu_scheduler *sched,
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struct amd_context_entity *c_entity,
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void *job)
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{
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int r = 0;
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struct amdgpu_cs_parser *sched_job = (struct amdgpu_cs_parser *)job;
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if (sched_job->prepare_job) {
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r = sched_job->prepare_job(sched_job);
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if (r) {
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DRM_ERROR("Prepare job error\n");
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schedule_work(&sched_job->job_work);
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}
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}
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return r;
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}
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static void amdgpu_fence_sched_cb(struct fence *f, struct fence_cb *cb)
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{
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struct amdgpu_fence *fence =
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container_of(cb, struct amdgpu_fence, cb);
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amd_sched_isr(fence->ring->scheduler);
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}
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static void amdgpu_sched_run_job(struct amd_gpu_scheduler *sched,
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struct amd_context_entity *c_entity,
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void *job)
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{
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int r = 0;
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struct amdgpu_cs_parser *sched_job = (struct amdgpu_cs_parser *)job;
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struct amdgpu_fence *fence;
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mutex_lock(&sched_job->job_lock);
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r = amdgpu_ib_schedule(sched_job->adev,
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sched_job->num_ibs,
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sched_job->ibs,
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sched_job->filp);
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if (r)
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goto err;
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fence = sched_job->ibs[sched_job->num_ibs - 1].fence;
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if (fence_add_callback(&fence->base,
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&fence->cb, amdgpu_fence_sched_cb))
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goto err;
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if (sched_job->run_job) {
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r = sched_job->run_job(sched_job);
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if (r)
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goto err;
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}
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amd_sched_emit(c_entity, sched_job->ibs[sched_job->num_ibs - 1].sequence);
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mutex_unlock(&sched_job->job_lock);
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return;
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err:
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DRM_ERROR("Run job error\n");
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mutex_unlock(&sched_job->job_lock);
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schedule_work(&sched_job->job_work);
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}
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static void amdgpu_sched_process_job(struct amd_gpu_scheduler *sched, void *job)
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{
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struct amdgpu_cs_parser *sched_job = NULL;
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struct amdgpu_fence *fence = NULL;
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struct amdgpu_ring *ring = NULL;
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struct amdgpu_device *adev = NULL;
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if (!job)
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return;
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sched_job = (struct amdgpu_cs_parser *)job;
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fence = sched_job->ibs[sched_job->num_ibs - 1].fence;
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if (!fence)
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return;
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ring = fence->ring;
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adev = ring->adev;
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schedule_work(&sched_job->job_work);
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}
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struct amd_sched_backend_ops amdgpu_sched_ops = {
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.prepare_job = amdgpu_sched_prepare_job,
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.run_job = amdgpu_sched_run_job,
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.process_job = amdgpu_sched_process_job
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};
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int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
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struct amdgpu_ring *ring,
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struct amdgpu_ib *ibs,
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unsigned num_ibs,
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int (*free_job)(struct amdgpu_cs_parser *),
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void *owner,
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struct fence **f)
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{
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int r = 0;
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if (amdgpu_enable_scheduler) {
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struct amdgpu_cs_parser *sched_job =
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amdgpu_cs_parser_create(adev, owner, &adev->kernel_ctx,
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ibs, 1);
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if(!sched_job) {
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return -ENOMEM;
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}
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sched_job->free_job = free_job;
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ibs[num_ibs - 1].sequence = amd_sched_push_job(ring->scheduler,
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&adev->kernel_ctx.rings[ring->idx].c_entity,
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sched_job);
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r = amd_sched_wait_emit(
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&adev->kernel_ctx.rings[ring->idx].c_entity,
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ibs[num_ibs - 1].sequence, false, -1);
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if (r)
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WARN(true, "emit timeout\n");
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} else
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r = amdgpu_ib_schedule(adev, 1, ibs, owner);
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if (r)
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return r;
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*f = &ibs[num_ibs - 1].fence->base;
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return 0;
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}
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