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The Non-HD Audio Endpoint Description table contains the link configuration information for the DSP. This is specific to Non HDA links only, like I2s and PDM Skylake driver will use NHLT table to retrieve the configuration based on the link type, format, channel and rate. This configuration is passed to DSP FW Signed-off-by: Jeeja KP <jeeja.kp@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
79 lines
2.3 KiB
C
79 lines
2.3 KiB
C
/*
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* skl.h - HD Audio skylake defintions.
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*
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* Copyright (C) 2015 Intel Corp
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* Author: Jeeja KP <jeeja.kp@intel.com>
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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*/
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#ifndef __SOUND_SOC_SKL_H
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#define __SOUND_SOC_SKL_H
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#include <sound/hda_register.h>
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#include <sound/hdaudio_ext.h>
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#include "skl-nhlt.h"
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#define SKL_SUSPEND_DELAY 2000
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/* Vendor Specific Registers */
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#define AZX_REG_VS_EM1 0x1000
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#define AZX_REG_VS_INRC 0x1004
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#define AZX_REG_VS_OUTRC 0x1008
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#define AZX_REG_VS_FIFOTRK 0x100C
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#define AZX_REG_VS_FIFOTRK2 0x1010
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#define AZX_REG_VS_EM2 0x1030
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#define AZX_REG_VS_EM3L 0x1038
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#define AZX_REG_VS_EM3U 0x103C
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#define AZX_REG_VS_EM4L 0x1040
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#define AZX_REG_VS_EM4U 0x1044
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#define AZX_REG_VS_LTRC 0x1048
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#define AZX_REG_VS_D0I3C 0x104A
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#define AZX_REG_VS_PCE 0x104B
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#define AZX_REG_VS_L2MAGC 0x1050
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#define AZX_REG_VS_L2LAHPT 0x1054
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#define AZX_REG_VS_SDXDPIB_XBASE 0x1084
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#define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20
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#define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094
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#define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20
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struct skl {
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struct hdac_ext_bus ebus;
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struct pci_dev *pci;
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unsigned int init_failed:1; /* delayed init failed */
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struct platform_device *dmic_dev;
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void __iomem *nhlt; /* nhlt ptr */
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};
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#define skl_to_ebus(s) (&(s)->ebus)
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#define ebus_to_skl(sbus) \
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container_of(sbus, struct skl, sbus)
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/* to pass dai dma data */
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struct skl_dma_params {
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u32 format;
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u8 stream_tag;
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};
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int skl_platform_unregister(struct device *dev);
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int skl_platform_register(struct device *dev);
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void __iomem *skl_nhlt_init(struct device *dev);
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void skl_nhlt_free(void __iomem *addr);
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struct nhlt_specific_cfg *skl_get_ep_blob(struct skl *skl, u32 instance,
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u8 link_type, u8 s_fmt, u8 no_ch, u32 s_rate, u8 dirn);
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#endif /* __SOUND_SOC_SKL_H */
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