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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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596 lines
16 KiB
C
596 lines
16 KiB
C
/*
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* sata_nv.c - NVIDIA nForce SATA
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*
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* Copyright 2004 NVIDIA Corp. All rights reserved.
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* Copyright 2004 Andrew Chew
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/DocBook/libata.*
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*
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* No hardware documentation available outside of NVIDIA.
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* This driver programs the NVIDIA SATA controller in a similar
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* fashion as with other PCI IDE BMDMA controllers, with a few
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* NV-specific details such as register offsets, SATA phy location,
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* hotplug info, etc.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "sata_nv"
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#define DRV_VERSION "2.0"
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enum {
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NV_PORTS = 2,
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NV_PIO_MASK = 0x1f,
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NV_MWDMA_MASK = 0x07,
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NV_UDMA_MASK = 0x7f,
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NV_PORT0_SCR_REG_OFFSET = 0x00,
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NV_PORT1_SCR_REG_OFFSET = 0x40,
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/* INT_STATUS/ENABLE */
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NV_INT_STATUS = 0x10,
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NV_INT_ENABLE = 0x11,
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NV_INT_STATUS_CK804 = 0x440,
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NV_INT_ENABLE_CK804 = 0x441,
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/* INT_STATUS/ENABLE bits */
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NV_INT_DEV = 0x01,
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NV_INT_PM = 0x02,
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NV_INT_ADDED = 0x04,
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NV_INT_REMOVED = 0x08,
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NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */
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NV_INT_ALL = 0x0f,
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NV_INT_MASK = NV_INT_DEV |
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NV_INT_ADDED | NV_INT_REMOVED,
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/* INT_CONFIG */
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NV_INT_CONFIG = 0x12,
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NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
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// For PCI config register 20
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NV_MCP_SATA_CFG_20 = 0x50,
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NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
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};
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static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
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static void nv_ck804_host_stop(struct ata_host *host);
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static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance,
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struct pt_regs *regs);
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static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance,
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struct pt_regs *regs);
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static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance,
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struct pt_regs *regs);
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static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
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static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
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static void nv_nf2_freeze(struct ata_port *ap);
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static void nv_nf2_thaw(struct ata_port *ap);
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static void nv_ck804_freeze(struct ata_port *ap);
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static void nv_ck804_thaw(struct ata_port *ap);
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static void nv_error_handler(struct ata_port *ap);
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enum nv_host_type
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{
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GENERIC,
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NFORCE2,
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NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
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CK804
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};
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static const struct pci_device_id nv_pci_tbl[] = {
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
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{ PCI_VENDOR_ID_NVIDIA, 0x045c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
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{ PCI_VENDOR_ID_NVIDIA, 0x045d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
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{ PCI_VENDOR_ID_NVIDIA, 0x045e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
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{ PCI_VENDOR_ID_NVIDIA, 0x045f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
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{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
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PCI_ANY_ID, PCI_ANY_ID,
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PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
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{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
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PCI_ANY_ID, PCI_ANY_ID,
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PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
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{ 0, } /* terminate list */
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};
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static struct pci_driver nv_pci_driver = {
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.name = DRV_NAME,
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.id_table = nv_pci_tbl,
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.probe = nv_init_one,
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.remove = ata_pci_remove_one,
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};
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static struct scsi_host_template nv_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.slave_destroy = ata_scsi_slave_destroy,
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.bios_param = ata_std_bios_param,
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};
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static const struct ata_port_operations nv_generic_ops = {
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.port_disable = ata_port_disable,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.exec_command = ata_exec_command,
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.check_status = ata_check_status,
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.dev_select = ata_std_dev_select,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = nv_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.data_xfer = ata_pio_data_xfer,
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.irq_handler = nv_generic_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.scr_read = nv_scr_read,
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.scr_write = nv_scr_write,
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.port_start = ata_port_start,
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.port_stop = ata_port_stop,
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.host_stop = ata_pci_host_stop,
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};
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static const struct ata_port_operations nv_nf2_ops = {
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.port_disable = ata_port_disable,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.exec_command = ata_exec_command,
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.check_status = ata_check_status,
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.dev_select = ata_std_dev_select,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.freeze = nv_nf2_freeze,
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.thaw = nv_nf2_thaw,
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.error_handler = nv_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.data_xfer = ata_pio_data_xfer,
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.irq_handler = nv_nf2_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.scr_read = nv_scr_read,
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.scr_write = nv_scr_write,
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.port_start = ata_port_start,
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.port_stop = ata_port_stop,
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.host_stop = ata_pci_host_stop,
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};
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static const struct ata_port_operations nv_ck804_ops = {
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.port_disable = ata_port_disable,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.exec_command = ata_exec_command,
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.check_status = ata_check_status,
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.dev_select = ata_std_dev_select,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.freeze = nv_ck804_freeze,
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.thaw = nv_ck804_thaw,
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.error_handler = nv_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.data_xfer = ata_pio_data_xfer,
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.irq_handler = nv_ck804_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.scr_read = nv_scr_read,
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.scr_write = nv_scr_write,
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.port_start = ata_port_start,
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.port_stop = ata_port_stop,
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.host_stop = nv_ck804_host_stop,
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};
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static struct ata_port_info nv_port_info[] = {
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/* generic */
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{
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.sht = &nv_sht,
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.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
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.pio_mask = NV_PIO_MASK,
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.mwdma_mask = NV_MWDMA_MASK,
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.udma_mask = NV_UDMA_MASK,
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.port_ops = &nv_generic_ops,
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},
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/* nforce2/3 */
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{
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.sht = &nv_sht,
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.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
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.pio_mask = NV_PIO_MASK,
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.mwdma_mask = NV_MWDMA_MASK,
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.udma_mask = NV_UDMA_MASK,
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.port_ops = &nv_nf2_ops,
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},
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/* ck804 */
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{
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.sht = &nv_sht,
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.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
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.pio_mask = NV_PIO_MASK,
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.mwdma_mask = NV_MWDMA_MASK,
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.udma_mask = NV_UDMA_MASK,
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.port_ops = &nv_ck804_ops,
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},
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};
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MODULE_AUTHOR("NVIDIA");
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MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
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MODULE_VERSION(DRV_VERSION);
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static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance,
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struct pt_regs *regs)
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{
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struct ata_host *host = dev_instance;
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unsigned int i;
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unsigned int handled = 0;
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unsigned long flags;
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spin_lock_irqsave(&host->lock, flags);
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for (i = 0; i < host->n_ports; i++) {
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struct ata_port *ap;
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ap = host->ports[i];
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if (ap &&
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!(ap->flags & ATA_FLAG_DISABLED)) {
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struct ata_queued_cmd *qc;
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qc = ata_qc_from_tag(ap, ap->active_tag);
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if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
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handled += ata_host_intr(ap, qc);
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else
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// No request pending? Clear interrupt status
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// anyway, in case there's one pending.
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ap->ops->check_status(ap);
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}
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}
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spin_unlock_irqrestore(&host->lock, flags);
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return IRQ_RETVAL(handled);
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}
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static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
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{
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struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
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int handled;
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/* freeze if hotplugged */
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if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) {
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ata_port_freeze(ap);
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return 1;
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}
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/* bail out if not our interrupt */
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if (!(irq_stat & NV_INT_DEV))
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return 0;
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/* DEV interrupt w/ no active qc? */
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if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
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ata_check_status(ap);
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return 1;
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}
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/* handle interrupt */
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handled = ata_host_intr(ap, qc);
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if (unlikely(!handled)) {
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/* spurious, clear it */
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ata_check_status(ap);
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}
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return 1;
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}
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static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat)
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{
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int i, handled = 0;
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for (i = 0; i < host->n_ports; i++) {
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struct ata_port *ap = host->ports[i];
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if (ap && !(ap->flags & ATA_FLAG_DISABLED))
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handled += nv_host_intr(ap, irq_stat);
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irq_stat >>= NV_INT_PORT_SHIFT;
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}
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return IRQ_RETVAL(handled);
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}
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static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance,
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struct pt_regs *regs)
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{
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struct ata_host *host = dev_instance;
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u8 irq_stat;
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irqreturn_t ret;
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spin_lock(&host->lock);
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irq_stat = inb(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
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ret = nv_do_interrupt(host, irq_stat);
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spin_unlock(&host->lock);
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return ret;
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}
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static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance,
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struct pt_regs *regs)
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{
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struct ata_host *host = dev_instance;
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u8 irq_stat;
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irqreturn_t ret;
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spin_lock(&host->lock);
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irq_stat = readb(host->mmio_base + NV_INT_STATUS_CK804);
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ret = nv_do_interrupt(host, irq_stat);
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spin_unlock(&host->lock);
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return ret;
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}
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static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
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{
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if (sc_reg > SCR_CONTROL)
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return 0xffffffffU;
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return ioread32((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
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}
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static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
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{
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if (sc_reg > SCR_CONTROL)
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return;
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iowrite32(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
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}
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static void nv_nf2_freeze(struct ata_port *ap)
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{
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unsigned long scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
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int shift = ap->port_no * NV_INT_PORT_SHIFT;
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u8 mask;
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mask = inb(scr_addr + NV_INT_ENABLE);
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mask &= ~(NV_INT_ALL << shift);
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outb(mask, scr_addr + NV_INT_ENABLE);
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}
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static void nv_nf2_thaw(struct ata_port *ap)
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{
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unsigned long scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
|
|
int shift = ap->port_no * NV_INT_PORT_SHIFT;
|
|
u8 mask;
|
|
|
|
outb(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS);
|
|
|
|
mask = inb(scr_addr + NV_INT_ENABLE);
|
|
mask |= (NV_INT_MASK << shift);
|
|
outb(mask, scr_addr + NV_INT_ENABLE);
|
|
}
|
|
|
|
static void nv_ck804_freeze(struct ata_port *ap)
|
|
{
|
|
void __iomem *mmio_base = ap->host->mmio_base;
|
|
int shift = ap->port_no * NV_INT_PORT_SHIFT;
|
|
u8 mask;
|
|
|
|
mask = readb(mmio_base + NV_INT_ENABLE_CK804);
|
|
mask &= ~(NV_INT_ALL << shift);
|
|
writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
|
|
}
|
|
|
|
static void nv_ck804_thaw(struct ata_port *ap)
|
|
{
|
|
void __iomem *mmio_base = ap->host->mmio_base;
|
|
int shift = ap->port_no * NV_INT_PORT_SHIFT;
|
|
u8 mask;
|
|
|
|
writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);
|
|
|
|
mask = readb(mmio_base + NV_INT_ENABLE_CK804);
|
|
mask |= (NV_INT_MASK << shift);
|
|
writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
|
|
}
|
|
|
|
static int nv_hardreset(struct ata_port *ap, unsigned int *class)
|
|
{
|
|
unsigned int dummy;
|
|
|
|
/* SATA hardreset fails to retrieve proper device signature on
|
|
* some controllers. Don't classify on hardreset. For more
|
|
* info, see http://bugme.osdl.org/show_bug.cgi?id=3352
|
|
*/
|
|
return sata_std_hardreset(ap, &dummy);
|
|
}
|
|
|
|
static void nv_error_handler(struct ata_port *ap)
|
|
{
|
|
ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
|
|
nv_hardreset, ata_std_postreset);
|
|
}
|
|
|
|
static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
{
|
|
static int printed_version = 0;
|
|
struct ata_port_info *ppi[2];
|
|
struct ata_probe_ent *probe_ent;
|
|
int pci_dev_busy = 0;
|
|
int rc;
|
|
u32 bar;
|
|
unsigned long base;
|
|
|
|
// Make sure this is a SATA controller by counting the number of bars
|
|
// (NVIDIA SATA controllers will always have six bars). Otherwise,
|
|
// it's an IDE controller and we ignore it.
|
|
for (bar=0; bar<6; bar++)
|
|
if (pci_resource_start(pdev, bar) == 0)
|
|
return -ENODEV;
|
|
|
|
if (!printed_version++)
|
|
dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
|
|
|
|
rc = pci_enable_device(pdev);
|
|
if (rc)
|
|
goto err_out;
|
|
|
|
rc = pci_request_regions(pdev, DRV_NAME);
|
|
if (rc) {
|
|
pci_dev_busy = 1;
|
|
goto err_out_disable;
|
|
}
|
|
|
|
rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
|
|
if (rc)
|
|
goto err_out_regions;
|
|
rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
|
|
if (rc)
|
|
goto err_out_regions;
|
|
|
|
rc = -ENOMEM;
|
|
|
|
ppi[0] = ppi[1] = &nv_port_info[ent->driver_data];
|
|
probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
|
|
if (!probe_ent)
|
|
goto err_out_regions;
|
|
|
|
probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
|
|
if (!probe_ent->mmio_base) {
|
|
rc = -EIO;
|
|
goto err_out_free_ent;
|
|
}
|
|
|
|
base = (unsigned long)probe_ent->mmio_base;
|
|
|
|
probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
|
|
probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
|
|
|
|
/* enable SATA space for CK804 */
|
|
if (ent->driver_data == CK804) {
|
|
u8 regval;
|
|
|
|
pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val);
|
|
regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
|
|
pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
|
|
}
|
|
|
|
pci_set_master(pdev);
|
|
|
|
rc = ata_device_add(probe_ent);
|
|
if (rc != NV_PORTS)
|
|
goto err_out_iounmap;
|
|
|
|
kfree(probe_ent);
|
|
|
|
return 0;
|
|
|
|
err_out_iounmap:
|
|
pci_iounmap(pdev, probe_ent->mmio_base);
|
|
err_out_free_ent:
|
|
kfree(probe_ent);
|
|
err_out_regions:
|
|
pci_release_regions(pdev);
|
|
err_out_disable:
|
|
if (!pci_dev_busy)
|
|
pci_disable_device(pdev);
|
|
err_out:
|
|
return rc;
|
|
}
|
|
|
|
static void nv_ck804_host_stop(struct ata_host *host)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(host->dev);
|
|
u8 regval;
|
|
|
|
/* disable SATA space for CK804 */
|
|
pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val);
|
|
regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
|
|
pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
|
|
|
|
ata_pci_host_stop(host);
|
|
}
|
|
|
|
static int __init nv_init(void)
|
|
{
|
|
return pci_register_driver(&nv_pci_driver);
|
|
}
|
|
|
|
static void __exit nv_exit(void)
|
|
{
|
|
pci_unregister_driver(&nv_pci_driver);
|
|
}
|
|
|
|
module_init(nv_init);
|
|
module_exit(nv_exit);
|