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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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dc37374b9c
It makes no sense that some Freescale device tree files are in fsl directory while some others not. This patch move Freescale device tree files into fsl folder. To do that the following two steps are made: - Move Freescale device tree files into fsl folder. - Update the include path in these files from "fsl/*.dtsi" to "*.dtsi". Please add "fsl/" prefix when you make dtb using Makefile. Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com> [scottwood: fixed cuImage rule] Signed-off-by: Scott Wood <scottwood@freescale.com>
293 lines
7.0 KiB
Plaintext
293 lines
7.0 KiB
Plaintext
/*
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* P1020 RDB-PD Device Tree Source (32-bit address map)
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*
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* Copyright 2013 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/include/ "p1020si-pre.dtsi"
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/ {
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model = "fsl,P1020RDB-PD";
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compatible = "fsl,P1020RDB-PD";
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memory {
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device_type = "memory";
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};
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lbc: localbus@ffe05000 {
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reg = <0x0 0xffe05000 0x0 0x1000>;
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/* NOR, NAND flash, L2 switch and CPLD */
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ranges = <0x0 0x0 0x0 0xec000000 0x04000000
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0x1 0x0 0x0 0xff800000 0x00040000
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0x2 0x0 0x0 0xffa00000 0x00020000
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0x3 0x0 0x0 0xffb00000 0x00020000>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x4000000>;
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bank-width = <2>;
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device-width = <1>;
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partition@0 {
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/* 128KB for DTB Image */
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reg = <0x0 0x00020000>;
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label = "NOR DTB Image";
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};
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partition@20000 {
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/* 3.875 MB for Linux Kernel Image */
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reg = <0x00020000 0x003e0000>;
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label = "NOR Linux Kernel Image";
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};
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partition@400000 {
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/* 58MB for Root file System */
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reg = <0x00400000 0x03a00000>;
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label = "NOR Root File System";
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};
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partition@3e00000 {
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/* This location must not be altered */
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/* 1M for Vitesse 7385 Switch firmware */
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reg = <0x3e00000 0x00100000>;
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label = "NOR Vitesse-7385 Firmware";
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read-only;
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};
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partition@3f00000 {
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/* This location must not be altered */
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/* 512KB for u-boot Bootloader Image */
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/* 512KB for u-boot Environment Variables */
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reg = <0x03f00000 0x00100000>;
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label = "NOR U-Boot Image";
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read-only;
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};
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};
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nand@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,p1020-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <0x1 0x0 0x40000>;
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partition@0 {
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/* This location must not be altered */
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/* 1MB for u-boot Bootloader Image */
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reg = <0x0 0x00100000>;
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label = "NAND U-Boot Image";
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read-only;
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};
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partition@100000 {
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/* 1MB for DTB Image */
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reg = <0x00100000 0x00100000>;
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label = "NAND DTB Image";
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};
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partition@200000 {
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/* 4MB for Linux Kernel Image */
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reg = <0x00200000 0x00400000>;
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label = "NAND Linux Kernel Image";
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};
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partition@600000 {
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/* 122MB for File System Image */
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reg = <0x00600000 0x07a00000>;
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label = "NAND File System Image";
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};
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};
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cpld@2,0 {
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compatible = "fsl,p1020rdb-pd-cpld";
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reg = <0x2 0x0 0x20000>;
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};
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L2switch@3,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "vitesse-7385";
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reg = <0x3 0x0 0x20000>;
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};
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};
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soc: soc@ffe00000 {
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ranges = <0x0 0x0 0xffe00000 0x100000>;
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i2c@3000 {
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rtc@68 {
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compatible = "dallas,ds1339";
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reg = <0x68>;
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};
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};
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spi@7000 {
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spansion,s25sl12801";
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reg = <0>;
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/* input clock */
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spi-max-frequency = <40000000>;
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partition@0 {
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/* 512KB for u-boot Bootloader Image */
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reg = <0x0 0x00080000>;
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label = "SPI U-Boot Image";
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read-only;
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};
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partition@80000 {
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/* 512KB for DTB Image*/
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reg = <0x00080000 0x00080000>;
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label = "SPI DTB Image";
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};
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partition@100000 {
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/* 4MB for Linux Kernel Image */
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reg = <0x00100000 0x00400000>;
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label = "SPI Linux Kernel Image";
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};
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partition@500000 {
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/* 11MB for FS System Image */
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reg = <0x00500000 0x00b00000>;
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label = "SPI File System Image";
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};
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};
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slic@0 {
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compatible = "zarlink,le88266";
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reg = <1>;
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spi-max-frequency = <8000000>;
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};
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slic@1 {
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compatible = "zarlink,le88266";
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reg = <2>;
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spi-max-frequency = <8000000>;
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};
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};
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mdio@24000 {
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phy0: ethernet-phy@0 {
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interrupts = <3 1 0 0>;
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reg = <0x0>;
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};
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phy1: ethernet-phy@1 {
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interrupts = <2 1 0 0>;
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reg = <0x1>;
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};
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};
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mdio@25000 {
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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mdio@26000 {
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tbi2: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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ptp_clock@b0e00 {
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compatible = "fsl,etsec-ptp";
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reg = <0xb0e00 0xb0>;
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interrupts = <68 2 0 0 69 2 0 0>;
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fsl,tclk-period = <10>;
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fsl,tmr-prsc = <2>;
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fsl,tmr-add = <0x80000016>;
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fsl,tmr-fiper1 = <999999990>;
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fsl,tmr-fiper2 = <99990>;
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fsl,max-adj = <199999999>;
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};
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enet0: ethernet@b0000 {
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fixed-link = <1 1 1000 0 0>;
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phy-connection-type = "rgmii-id";
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};
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enet1: ethernet@b1000 {
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phy-handle = <&phy0>;
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tbi-handle = <&tbi1>;
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phy-connection-type = "sgmii";
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};
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enet2: ethernet@b2000 {
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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};
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usb@22000 {
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phy_type = "ulpi";
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};
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};
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pci0: pcie@ffe09000 {
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reg = <0x0 0xffe09000 0x0 0x1000>;
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ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xa0000000
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0x2000000 0x0 0xa0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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pci1: pcie@ffe0a000 {
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reg = <0x0 0xffe0a000 0x0 0x1000>;
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ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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};
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/include/ "p1020si-post.dtsi"
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