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A simple fix to extend GICv2 CPU interface registers from 4K to 8K on AEMv8 FVP/RTSM models in order to support split priority drop and interrupt deactivation. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJYZn50AAoJEABBurwxfuKYlUYQAJ4qNonGGnzErQE7bdYS2M+A fB2R14lhDmCx9HZ7K3ld00x1gaKMJsh1uEU+WXpAt+AFEtJWEaEvWrxcBAY7fQRU HWs/127+AQgpvKEgVMyOCoc+jj80HipoRMCCzfTZYpbI3LxfvQ7OwV47JpnKmo92 KO/4KZRvODBkupEkMF27ZtrScipLvHsgaYo2H2M2V/AatZ2e1XwGa6r0dxSqauuR ZEc0C6i3ln8HGOikPwaf5o11MA+m4GHKPQJ55tRjjvn0dIxrh4rshvt+Fiu4h/eX ImYAtsJS0PhZhRoqamWcfpzKhHQyQF6K05lX2AGBpKEuYjURqSppnndi43oGPIXw WMe2uS6Ay6Xs9X/viBEJY5B4Cs6STVBVKERJGglHktHn2RGlzLS47XINH/yvOjiv cbMqTe/PMYgh13QwpQjcuVkgDqhG2LlxueHaptEmJAW0X+juJQVgvSdmb359pn3O sq+4omo3Z7KnHjBAwDOHVOB9fqTMLNJ/E9MIqEjZ1JrbMmI6C+JUxHBYJ9+Rm9jc iSkgW1B9I/0lr5kNFLdsvvi9o5yPouZZvOB7DQoj8wnY0NqvmEVNLSRiCsuU4BkT SFIxo+BK+jLrlAf6imB7jPpl8pM3KL0/BpsvBFRdq7iI7KNUxlPneQNKXYQO1sii Gh1HgcgTCylRbPqYXhDD =BoKJ -----END PGP SIGNATURE----- Merge tag 'juno-fixes-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into fixes Pull "ARMv8 Juno/VExpress fixes for v4.10" from Sudeep Holla: A simple fix to extend GICv2 CPU interface registers from 4K to 8K on AEMv8 FVP/RTSM models in order to support split priority drop and interrupt deactivation. * tag 'juno-fixes-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: vexpress: Support GICC_DIR operations |
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allwinner | ||
altera | ||
amd | ||
amlogic | ||
apm | ||
arm | ||
broadcom | ||
cavium | ||
exynos | ||
freescale | ||
hisilicon | ||
include | ||
lg | ||
marvell | ||
mediatek | ||
nvidia | ||
qcom | ||
renesas | ||
rockchip | ||
socionext | ||
sprd | ||
xilinx | ||
zte | ||
.gitignore | ||
Makefile |