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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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08344f3b43
This is a collection of a few late fixes and other misc. stuff that had dependencies on things being merged from other trees. The Renesas R-Car power domain handling, and the Nvidia Tegra USB support both hand notable changes that required changing the DT binding in a way that only provides compatibility with old DT blobs on new kernels but not vice versa. As a consequence, the DT changes are based on top of the driver changes and are now in this branch. For NXP i.MX and Samsung Exynos, the changes in here depend on other changes that got merged through the clk maintainer tree. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIVAwUAV0Sse2CrR//JCVInAQJoOg//VQwAUxayKGfYVzhJjhHdYbVA9kWYczHb wizFbF51XPylQzfGgHxEZJgdO3y2Ks54J7xaCK7oSUPEBT0rHsLQunHhq0aVQpew 1c06vEysYMkRclG7C0zN7i4gwdig+L4r6kUguTvb+nyJS3RISg0LaSoANVU65dQ5 +g4DLRrX1QlZPBXR8Fc/S1gTFXU+dO1S0oJFnK9ZZTgmsGg4GA0qC60hdsv+WeSv uzS4FJoxSy9MzoAFqmnWIa4jBV9I1Rg5vi7dfoBbTW1XOAMpq+GVLLU+Lvso0Jqw xWjBSmPl6l/cZ7BhpzWq8knKOsEezh5LLrVRXViVCGfTIFdlObxyHzeKcJp25V1p mL98MBXobn9Rly9hJxyzpeNWITZ6qJYR+IQy3Lsuk5KrdZG2f4uTErtoqmYRI3Pn vuXoi13NUeoCrHZJZ+fNUGwx5a5/hgUQXP5u+98uucQSqIVxe0cGnQVnFm84X81r Sj/dXxFlFBZfqfE8rf1cFd+YEbKtpF13vEURAQWrnEzBmJSTu7Cp8qdA5hX5CeK4 DW9bsu5hkWwnzoC2Ox/ZQVms4aI3q8s2xuu28GEJJdCE2IUiSnag/5vhGBzd4dTm 9R69RhE9y4EOhw+0z1O0LfoKoo6YyUQa+OUNVIwEfFjcCdZiMQIdZWi2PLv4jeAR jBBbpcWtHLo= =I0Be -----END PGP SIGNATURE----- Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late DT updates from Arnd Bergmann: "This is a collection of a few late fixes and other misc stuff that had dependencies on things being merged from other trees. The Renesas R-Car power domain handling, and the Nvidia Tegra USB support both hand notable changes that required changing the DT binding in a way that only provides compatibility with old DT blobs on new kernels but not vice versa. As a consequence, the DT changes are based on top of the driver changes and are now in this branch. For NXP i.MX and Samsung Exynos, the changes in here depend on other changes that got merged through the clk maintainer tree" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (35 commits) ARM: dts: exynos: Add support of Bus frequency using VDD_INT for exynos5422-odroidxu3 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos542x SoC ARM: dts: exynos: Add NoC Probe dt node for Exynos542x SoC ARM: dts: exynos: Add support of bus frequency for exynos4412-trats/odroidu3 ARM: dts: exynos: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3 ARM: dts: exynos: Add support of bus frequency using VDD_INT for exynos3250-rinato ARM: dts: exynos: Add exynos4412-ppmu-common dtsi to delete duplicate PPMU nodes ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4210 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos4x12 ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4x12 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos3250 ARM: dts: exynos: Add DMC bus frequency for exynos3250-rinato/monk ARM: dts: exynos: Add DMC bus node for Exynos3250 ARM: tegra: Enable XUSB on Nyan ARM: tegra: Enable XUSB on Jetson TK1 ARM: tegra: Enable XUSB on Venice2 ARM: tegra: Add Tegra124 XUSB controller ARM: tegra: Move Tegra124 to the new XUSB pad controller binding ARM: dts: r8a7794: Use SYSC "always-on" PM Domain ARM: dts: r8a7793: Use SYSC "always-on" PM Domain ...
576 lines
14 KiB
Plaintext
576 lines
14 KiB
Plaintext
/*
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* Samsung's Exynos4x12 SoCs device tree source
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
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* based board files can include this file and provide values for board specfic
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* bindings.
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*
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* Note: This file does not include device nodes for all the controllers in
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* Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
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* nodes can be added to this file.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "exynos4.dtsi"
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#include "exynos4x12-pinctrl.dtsi"
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#include "exynos4-cpu-thermal.dtsi"
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/ {
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aliases {
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pinctrl0 = &pinctrl_0;
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pinctrl1 = &pinctrl_1;
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pinctrl2 = &pinctrl_2;
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pinctrl3 = &pinctrl_3;
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fimc-lite0 = &fimc_lite_0;
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fimc-lite1 = &fimc_lite_1;
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mshc0 = &mshc_0;
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};
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sysram@02020000 {
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compatible = "mmio-sram";
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reg = <0x02020000 0x40000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x02020000 0x40000>;
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smp-sysram@0 {
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compatible = "samsung,exynos4210-sysram";
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reg = <0x0 0x1000>;
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};
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smp-sysram@2f000 {
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compatible = "samsung,exynos4210-sysram-ns";
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reg = <0x2f000 0x1000>;
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};
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};
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pd_isp: isp-power-domain@10023CA0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10023CA0 0x20>;
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#power-domain-cells = <0>;
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};
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l2c: l2-cache-controller@10502000 {
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compatible = "arm,pl310-cache";
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reg = <0x10502000 0x1000>;
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cache-unified;
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cache-level = <2>;
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arm,tag-latency = <2 2 1>;
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arm,data-latency = <3 2 1>;
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arm,double-linefill = <1>;
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arm,double-linefill-incr = <0>;
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arm,double-linefill-wrap = <1>;
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arm,prefetch-drop = <1>;
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arm,prefetch-offset = <7>;
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};
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clock: clock-controller@10030000 {
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compatible = "samsung,exynos4412-clock";
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reg = <0x10030000 0x20000>;
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#clock-cells = <1>;
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};
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mct@10050000 {
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compatible = "samsung,exynos4412-mct";
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reg = <0x10050000 0x800>;
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interrupt-parent = <&mct_map>;
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interrupts = <0>, <1>, <2>, <3>, <4>;
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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clock-names = "fin_pll", "mct";
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mct_map: mct-map {
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = <0 &gic 0 57 0>,
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<1 &combiner 12 5>,
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<2 &combiner 12 6>,
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<3 &combiner 12 7>,
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<4 &gic 1 12 0>;
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};
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};
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adc: adc@126C0000 {
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compatible = "samsung,exynos-adc-v1";
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reg = <0x126C0000 0x100>;
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interrupt-parent = <&combiner>;
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interrupts = <10 3>;
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clocks = <&clock CLK_TSADC>;
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clock-names = "adc";
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#io-channel-cells = <1>;
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io-channel-ranges;
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samsung,syscon-phandle = <&pmu_system_controller>;
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status = "disabled";
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};
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g2d: g2d@10800000 {
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compatible = "samsung,exynos4212-g2d";
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reg = <0x10800000 0x1000>;
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interrupts = <0 89 0>;
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clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
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clock-names = "sclk_fimg2d", "fimg2d";
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iommus = <&sysmmu_g2d>;
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};
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camera {
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clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
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<&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
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clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
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/* fimc_[0-3] are configured outside, under phandles */
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fimc_lite_0: fimc-lite@12390000 {
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compatible = "samsung,exynos4212-fimc-lite";
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reg = <0x12390000 0x1000>;
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interrupts = <0 105 0>;
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power-domains = <&pd_isp>;
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clocks = <&clock CLK_FIMC_LITE0>;
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clock-names = "flite";
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iommus = <&sysmmu_fimc_lite0>;
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status = "disabled";
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};
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fimc_lite_1: fimc-lite@123A0000 {
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compatible = "samsung,exynos4212-fimc-lite";
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reg = <0x123A0000 0x1000>;
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interrupts = <0 106 0>;
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power-domains = <&pd_isp>;
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clocks = <&clock CLK_FIMC_LITE1>;
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clock-names = "flite";
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iommus = <&sysmmu_fimc_lite1>;
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status = "disabled";
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};
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fimc_is: fimc-is@12000000 {
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compatible = "samsung,exynos4212-fimc-is", "simple-bus";
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reg = <0x12000000 0x260000>;
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interrupts = <0 90 0>, <0 95 0>;
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power-domains = <&pd_isp>;
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clocks = <&clock CLK_FIMC_LITE0>,
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<&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
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<&clock CLK_PPMUISPMX>,
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<&clock CLK_MOUT_MPLL_USER_T>,
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<&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
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<&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
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<&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
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<&clock CLK_DIV_MCUISP0>,
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<&clock CLK_DIV_MCUISP1>,
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<&clock CLK_UART_ISP_SCLK>,
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<&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
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<&clock CLK_ACLK400_MCUISP>,
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<&clock CLK_DIV_ACLK400_MCUISP>;
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clock-names = "lite0", "lite1", "ppmuispx",
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"ppmuispmx", "mpll", "isp",
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"drc", "fd", "mcuisp",
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"ispdiv0", "ispdiv1", "mcuispdiv0",
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"mcuispdiv1", "uart", "aclk200",
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"div_aclk200", "aclk400mcuisp",
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"div_aclk400mcuisp";
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iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
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<&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
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iommu-names = "isp", "drc", "fd", "mcuctl";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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pmu@10020000 {
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reg = <0x10020000 0x3000>;
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};
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i2c1_isp: i2c-isp@12140000 {
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compatible = "samsung,exynos4212-i2c-isp";
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reg = <0x12140000 0x100>;
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clocks = <&clock CLK_I2C1_ISP>;
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clock-names = "i2c_isp";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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mshc_0: mmc@12550000 {
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compatible = "samsung,exynos4412-dw-mshc";
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reg = <0x12550000 0x1000>;
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interrupts = <0 77 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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fifo-depth = <0x80>;
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clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
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clock-names = "biu", "ciu";
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status = "disabled";
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};
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sysmmu_g2d: sysmmu@10A40000{
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compatible = "samsung,exynos-sysmmu";
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reg = <0x10A40000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <4 7>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_isp: sysmmu@12260000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x12260000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <16 2>;
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power-domains = <&pd_isp>;
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clock-names = "sysmmu";
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clocks = <&clock CLK_SMMU_ISP>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_drc: sysmmu@12270000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x12270000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <16 3>;
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power-domains = <&pd_isp>;
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clock-names = "sysmmu";
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clocks = <&clock CLK_SMMU_DRC>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_fd: sysmmu@122A0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x122A0000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <16 4>;
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power-domains = <&pd_isp>;
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clock-names = "sysmmu";
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clocks = <&clock CLK_SMMU_FD>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_mcuctl: sysmmu@122B0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x122B0000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <16 5>;
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power-domains = <&pd_isp>;
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clock-names = "sysmmu";
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clocks = <&clock CLK_SMMU_ISPCX>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_lite0: sysmmu@123B0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x123B0000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <16 0>;
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power-domains = <&pd_isp>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_lite1: sysmmu@123C0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x123C0000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <16 1>;
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power-domains = <&pd_isp>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
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#iommu-cells = <0>;
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};
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bus_dmc: bus_dmc {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_DMC>;
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clock-names = "bus";
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operating-points-v2 = <&bus_dmc_opp_table>;
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status = "disabled";
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};
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bus_acp: bus_acp {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_ACP>;
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clock-names = "bus";
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operating-points-v2 = <&bus_acp_opp_table>;
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status = "disabled";
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};
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bus_c2c: bus_c2c {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_C2C>;
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clock-names = "bus";
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operating-points-v2 = <&bus_dmc_opp_table>;
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status = "disabled";
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};
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bus_dmc_opp_table: opp_table1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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opp-microvolt = <900000>;
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};
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opp@134000000 {
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opp-hz = /bits/ 64 <134000000>;
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opp-microvolt = <900000>;
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};
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opp@160000000 {
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opp-hz = /bits/ 64 <160000000>;
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opp-microvolt = <900000>;
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};
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opp@267000000 {
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opp-hz = /bits/ 64 <267000000>;
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opp-microvolt = <950000>;
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};
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opp@400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <1050000>;
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};
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};
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bus_acp_opp_table: opp_table2 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp@134000000 {
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opp-hz = /bits/ 64 <134000000>;
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};
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opp@160000000 {
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opp-hz = /bits/ 64 <160000000>;
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};
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opp@267000000 {
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opp-hz = /bits/ 64 <267000000>;
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};
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};
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bus_leftbus: bus_leftbus {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_GDL>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_rightbus: bus_rightbus {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_GDR>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_display: bus_display {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK160>;
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clock-names = "bus";
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operating-points-v2 = <&bus_display_opp_table>;
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status = "disabled";
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};
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bus_fsys: bus_fsys {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK133>;
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clock-names = "bus";
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operating-points-v2 = <&bus_fsys_opp_table>;
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status = "disabled";
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};
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bus_peri: bus_peri {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK100>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_peri_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_mfc: bus_mfc {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_SCLK_MFC>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_leftbus_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_leftbus_opp_table: opp_table3 {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp@100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
opp-microvolt = <900000>;
|
|
};
|
|
opp@134000000 {
|
|
opp-hz = /bits/ 64 <134000000>;
|
|
opp-microvolt = <925000>;
|
|
};
|
|
opp@160000000 {
|
|
opp-hz = /bits/ 64 <160000000>;
|
|
opp-microvolt = <950000>;
|
|
};
|
|
opp@200000000 {
|
|
opp-hz = /bits/ 64 <200000000>;
|
|
opp-microvolt = <1000000>;
|
|
};
|
|
};
|
|
|
|
bus_display_opp_table: opp_table4 {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp@160000000 {
|
|
opp-hz = /bits/ 64 <160000000>;
|
|
};
|
|
opp@200000000 {
|
|
opp-hz = /bits/ 64 <200000000>;
|
|
};
|
|
};
|
|
|
|
bus_fsys_opp_table: opp_table5 {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp@100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
};
|
|
opp@134000000 {
|
|
opp-hz = /bits/ 64 <134000000>;
|
|
};
|
|
};
|
|
|
|
bus_peri_opp_table: opp_table6 {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp@50000000 {
|
|
opp-hz = /bits/ 64 <50000000>;
|
|
};
|
|
opp@100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&combiner {
|
|
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
|
|
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
|
|
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
|
|
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
|
|
<0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
|
|
};
|
|
|
|
&exynos_usbphy {
|
|
compatible = "samsung,exynos4x12-usb2-phy";
|
|
samsung,sysreg-phandle = <&sys_reg>;
|
|
};
|
|
|
|
&fimc_0 {
|
|
compatible = "samsung,exynos4212-fimc";
|
|
samsung,pix-limits = <4224 8192 1920 4224>;
|
|
samsung,mainscaler-ext;
|
|
samsung,isp-wb;
|
|
samsung,cam-if;
|
|
};
|
|
|
|
&fimc_1 {
|
|
compatible = "samsung,exynos4212-fimc";
|
|
samsung,pix-limits = <4224 8192 1920 4224>;
|
|
samsung,mainscaler-ext;
|
|
samsung,isp-wb;
|
|
samsung,cam-if;
|
|
};
|
|
|
|
&fimc_2 {
|
|
compatible = "samsung,exynos4212-fimc";
|
|
samsung,pix-limits = <4224 8192 1920 4224>;
|
|
samsung,mainscaler-ext;
|
|
samsung,isp-wb;
|
|
samsung,lcd-wb;
|
|
samsung,cam-if;
|
|
};
|
|
|
|
&fimc_3 {
|
|
compatible = "samsung,exynos4212-fimc";
|
|
samsung,pix-limits = <1920 8192 1366 1920>;
|
|
samsung,rotators = <0>;
|
|
samsung,mainscaler-ext;
|
|
samsung,isp-wb;
|
|
samsung,lcd-wb;
|
|
};
|
|
|
|
&hdmi {
|
|
compatible = "samsung,exynos4212-hdmi";
|
|
};
|
|
|
|
&jpeg_codec {
|
|
compatible = "samsung,exynos4212-jpeg";
|
|
};
|
|
|
|
&rotator {
|
|
compatible = "samsung,exynos4212-rotator";
|
|
};
|
|
|
|
&mixer {
|
|
compatible = "samsung,exynos4212-mixer";
|
|
clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
|
|
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
|
|
<&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
|
|
};
|
|
|
|
&pinctrl_0 {
|
|
compatible = "samsung,exynos4x12-pinctrl";
|
|
reg = <0x11400000 0x1000>;
|
|
interrupts = <0 47 0>;
|
|
};
|
|
|
|
&pinctrl_1 {
|
|
compatible = "samsung,exynos4x12-pinctrl";
|
|
reg = <0x11000000 0x1000>;
|
|
interrupts = <0 46 0>;
|
|
|
|
wakup_eint: wakeup-interrupt-controller {
|
|
compatible = "samsung,exynos4210-wakeup-eint";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 32 0>;
|
|
};
|
|
};
|
|
|
|
&pinctrl_2 {
|
|
compatible = "samsung,exynos4x12-pinctrl";
|
|
reg = <0x03860000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <10 0>;
|
|
};
|
|
|
|
&pinctrl_3 {
|
|
compatible = "samsung,exynos4x12-pinctrl";
|
|
reg = <0x106E0000 0x1000>;
|
|
interrupts = <0 72 0>;
|
|
};
|
|
|
|
&pmu_system_controller {
|
|
compatible = "samsung,exynos4212-pmu", "syscon";
|
|
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
|
|
"clkout4", "clkout8", "clkout9";
|
|
clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
|
|
<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
|
|
<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
&tmu {
|
|
compatible = "samsung,exynos4412-tmu";
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <2 4>;
|
|
reg = <0x100C0000 0x100>;
|
|
clocks = <&clock 383>;
|
|
clock-names = "tmu_apbif";
|
|
status = "disabled";
|
|
};
|