mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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955a3fc6d2
Having only 32 memslots is a real constraint for the maximum number of PCI devices that can be assigned to a single guest. Assuming each PCI device/virtual function having two memory BAR regions, we could assign only 15 devices/virtual functions to a guest. Hence increase KVM_USER_MEM_SLOTS to 512 as done in other archs like powerpc. Reviewed-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Linu Cherian <linu.cherian@cavium.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
398 lines
13 KiB
C
398 lines
13 KiB
C
/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Derived from arch/arm/include/asm/kvm_host.h:
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ARM64_KVM_HOST_H__
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#define __ARM64_KVM_HOST_H__
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#include <linux/types.h>
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#include <linux/kvm_types.h>
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#include <asm/kvm.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_mmio.h>
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#define __KVM_HAVE_ARCH_INTC_INITIALIZED
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#define KVM_USER_MEM_SLOTS 512
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#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
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#define KVM_HALT_POLL_NS_DEFAULT 500000
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#include <kvm/arm_vgic.h>
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#include <kvm/arm_arch_timer.h>
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#include <kvm/arm_pmu.h>
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#define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
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#define KVM_VCPU_MAX_FEATURES 4
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#define KVM_REQ_VCPU_EXIT 8
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int __attribute_const__ kvm_target_cpu(void);
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int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
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int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext);
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void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start);
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struct kvm_arch {
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/* The VMID generation used for the virt. memory system */
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u64 vmid_gen;
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u32 vmid;
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/* 1-level 2nd stage table and lock */
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spinlock_t pgd_lock;
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pgd_t *pgd;
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/* VTTBR value associated with above pgd and vmid */
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u64 vttbr;
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/* The last vcpu id that ran on each physical CPU */
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int __percpu *last_vcpu_ran;
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/* The maximum number of vCPUs depends on the used GIC model */
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int max_vcpus;
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/* Interrupt controller */
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struct vgic_dist vgic;
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};
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#define KVM_NR_MEM_OBJS 40
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/*
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* We don't want allocation failures within the mmu code, so we preallocate
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* enough memory for a single page fault in a cache.
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*/
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struct kvm_mmu_memory_cache {
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int nobjs;
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void *objects[KVM_NR_MEM_OBJS];
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};
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struct kvm_vcpu_fault_info {
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u32 esr_el2; /* Hyp Syndrom Register */
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u64 far_el2; /* Hyp Fault Address Register */
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u64 hpfar_el2; /* Hyp IPA Fault Address Register */
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};
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/*
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* 0 is reserved as an invalid value.
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* Order should be kept in sync with the save/restore code.
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*/
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enum vcpu_sysreg {
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__INVALID_SYSREG__,
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MPIDR_EL1, /* MultiProcessor Affinity Register */
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CSSELR_EL1, /* Cache Size Selection Register */
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SCTLR_EL1, /* System Control Register */
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ACTLR_EL1, /* Auxiliary Control Register */
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CPACR_EL1, /* Coprocessor Access Control */
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TTBR0_EL1, /* Translation Table Base Register 0 */
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TTBR1_EL1, /* Translation Table Base Register 1 */
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TCR_EL1, /* Translation Control Register */
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ESR_EL1, /* Exception Syndrome Register */
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AFSR0_EL1, /* Auxiliary Fault Status Register 0 */
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AFSR1_EL1, /* Auxiliary Fault Status Register 1 */
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FAR_EL1, /* Fault Address Register */
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MAIR_EL1, /* Memory Attribute Indirection Register */
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VBAR_EL1, /* Vector Base Address Register */
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CONTEXTIDR_EL1, /* Context ID Register */
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TPIDR_EL0, /* Thread ID, User R/W */
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TPIDRRO_EL0, /* Thread ID, User R/O */
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TPIDR_EL1, /* Thread ID, Privileged */
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AMAIR_EL1, /* Aux Memory Attribute Indirection Register */
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CNTKCTL_EL1, /* Timer Control Register (EL1) */
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PAR_EL1, /* Physical Address Register */
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MDSCR_EL1, /* Monitor Debug System Control Register */
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MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
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/* Performance Monitors Registers */
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PMCR_EL0, /* Control Register */
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PMSELR_EL0, /* Event Counter Selection Register */
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PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
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PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
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PMCCNTR_EL0, /* Cycle Counter Register */
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PMEVTYPER0_EL0, /* Event Type Register (0-30) */
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PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
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PMCCFILTR_EL0, /* Cycle Count Filter Register */
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PMCNTENSET_EL0, /* Count Enable Set Register */
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PMINTENSET_EL1, /* Interrupt Enable Set Register */
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PMOVSSET_EL0, /* Overflow Flag Status Set Register */
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PMSWINC_EL0, /* Software Increment Register */
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PMUSERENR_EL0, /* User Enable Register */
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/* 32bit specific registers. Keep them at the end of the range */
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DACR32_EL2, /* Domain Access Control Register */
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IFSR32_EL2, /* Instruction Fault Status Register */
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FPEXC32_EL2, /* Floating-Point Exception Control Register */
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DBGVCR32_EL2, /* Debug Vector Catch Register */
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NR_SYS_REGS /* Nothing after this line! */
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};
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/* 32bit mapping */
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#define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
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#define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */
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#define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */
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#define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */
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#define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */
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#define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
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#define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */
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#define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
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#define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */
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#define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */
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#define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */
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#define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */
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#define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
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#define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
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#define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
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#define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */
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#define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
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#define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */
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#define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */
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#define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
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#define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
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#define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
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#define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */
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#define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */
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#define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
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#define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */
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#define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
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#define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
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#define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
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#define cp14_DBGDSCRext (MDSCR_EL1 * 2)
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#define cp14_DBGBCR0 (DBGBCR0_EL1 * 2)
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#define cp14_DBGBVR0 (DBGBVR0_EL1 * 2)
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#define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1)
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#define cp14_DBGWCR0 (DBGWCR0_EL1 * 2)
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#define cp14_DBGWVR0 (DBGWVR0_EL1 * 2)
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#define cp14_DBGDCCINT (MDCCINT_EL1 * 2)
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#define NR_COPRO_REGS (NR_SYS_REGS * 2)
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struct kvm_cpu_context {
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struct kvm_regs gp_regs;
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union {
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u64 sys_regs[NR_SYS_REGS];
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u32 copro[NR_COPRO_REGS];
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};
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};
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typedef struct kvm_cpu_context kvm_cpu_context_t;
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struct kvm_vcpu_arch {
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struct kvm_cpu_context ctxt;
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/* HYP configuration */
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u64 hcr_el2;
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u32 mdcr_el2;
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/* Exception Information */
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struct kvm_vcpu_fault_info fault;
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/* Guest debug state */
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u64 debug_flags;
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/*
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* We maintain more than a single set of debug registers to support
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* debugging the guest from the host and to maintain separate host and
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* guest state during world switches. vcpu_debug_state are the debug
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* registers of the vcpu as the guest sees them. host_debug_state are
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* the host registers which are saved and restored during
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* world switches. external_debug_state contains the debug
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* values we want to debug the guest. This is set via the
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* KVM_SET_GUEST_DEBUG ioctl.
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*
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* debug_ptr points to the set of debug registers that should be loaded
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* onto the hardware when running the guest.
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*/
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struct kvm_guest_debug_arch *debug_ptr;
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struct kvm_guest_debug_arch vcpu_debug_state;
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struct kvm_guest_debug_arch external_debug_state;
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/* Pointer to host CPU context */
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kvm_cpu_context_t *host_cpu_context;
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struct {
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/* {Break,watch}point registers */
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struct kvm_guest_debug_arch regs;
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/* Statistical profiling extension */
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u64 pmscr_el1;
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} host_debug_state;
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/* VGIC state */
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struct vgic_cpu vgic_cpu;
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struct arch_timer_cpu timer_cpu;
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struct kvm_pmu pmu;
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/*
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* Anything that is not used directly from assembly code goes
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* here.
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*/
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/*
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* Guest registers we preserve during guest debugging.
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*
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* These shadow registers are updated by the kvm_handle_sys_reg
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* trap handler if the guest accesses or updates them while we
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* are using guest debug.
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*/
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struct {
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u32 mdscr_el1;
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} guest_debug_preserved;
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/* vcpu power-off state */
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bool power_off;
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/* Don't run the guest (internal implementation need) */
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bool pause;
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/* IO related fields */
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struct kvm_decode mmio_decode;
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/* Interrupt related fields */
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u64 irq_lines; /* IRQ and FIQ levels */
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/* Cache some mmu pages needed inside spinlock regions */
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struct kvm_mmu_memory_cache mmu_page_cache;
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/* Target CPU and feature flags */
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int target;
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DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
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/* Detect first run of a vcpu */
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bool has_run_once;
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};
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#define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs)
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#define vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)])
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/*
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* CP14 and CP15 live in the same array, as they are backed by the
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* same system registers.
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*/
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#define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)])
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#define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)])
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#ifdef CONFIG_CPU_BIG_ENDIAN
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#define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r))
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#define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r) + 1)
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#else
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#define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r) + 1)
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#define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r))
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#endif
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struct kvm_vm_stat {
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ulong remote_tlb_flush;
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};
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struct kvm_vcpu_stat {
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u64 halt_successful_poll;
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u64 halt_attempted_poll;
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u64 halt_poll_invalid;
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u64 halt_wakeup;
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u64 hvc_exit_stat;
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u64 wfe_exit_stat;
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u64 wfi_exit_stat;
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u64 mmio_exit_user;
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u64 mmio_exit_kernel;
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u64 exits;
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};
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int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
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unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
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int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
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int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
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int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
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#define KVM_ARCH_WANT_MMU_NOTIFIER
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int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
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int kvm_unmap_hva_range(struct kvm *kvm,
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unsigned long start, unsigned long end);
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void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
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int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
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int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
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/* We do not have shadow page tables, hence the empty hooks */
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static inline void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
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unsigned long address)
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{
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}
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struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
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struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void);
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void kvm_arm_halt_guest(struct kvm *kvm);
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void kvm_arm_resume_guest(struct kvm *kvm);
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void kvm_arm_halt_vcpu(struct kvm_vcpu *vcpu);
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void kvm_arm_resume_vcpu(struct kvm_vcpu *vcpu);
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u64 __kvm_call_hyp(void *hypfn, ...);
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#define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__)
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void force_vm_exit(const cpumask_t *mask);
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void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);
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int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
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int exception_index);
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int kvm_perf_init(void);
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int kvm_perf_teardown(void);
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struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
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static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
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unsigned long hyp_stack_ptr,
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unsigned long vector_ptr)
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{
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/*
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* Call initialization code, and switch to the full blown
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* HYP code.
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*/
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__kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr);
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}
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void __kvm_hyp_teardown(void);
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static inline void __cpu_reset_hyp_mode(unsigned long vector_ptr,
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phys_addr_t phys_idmap_start)
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{
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kvm_call_hyp(__kvm_hyp_teardown, phys_idmap_start);
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}
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static inline void kvm_arch_hardware_unsetup(void) {}
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static inline void kvm_arch_sync_events(struct kvm *kvm) {}
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static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
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static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
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static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
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void kvm_arm_init_debug(void);
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void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
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void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
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void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
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int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr);
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int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr);
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int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr);
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static inline void __cpu_init_stage2(void)
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{
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u32 parange = kvm_call_hyp(__init_stage2_translation);
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WARN_ONCE(parange < 40,
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"PARange is %d bits, unsupported configuration!", parange);
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}
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#endif /* __ARM64_KVM_HOST_H__ */
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