mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 17:35:17 +07:00
96ae48b7fa
This patch is to allocate rx queue's memory based on numa node and also use page based buffers for rx traffic improvements. Signed-off-by: Derek Chickles <derek.chickles@caviumnetworks.com> Signed-off-by: Satanand Burla <satananda.burla@caviumnetworks.com> Signed-off-by: Felix Manlunas <felix.manlunas@caviumnetworks.com> Signed-off-by: Raghu Vatsavayi <raghu.vatsavayi@caviumnetworks.com> Signed-off-by: David S. Miller <davem@davemloft.net>
243 lines
6.0 KiB
C
243 lines
6.0 KiB
C
/**********************************************************************
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* Author: Cavium, Inc.
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*
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* Contact: support@cavium.com
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* Please include "LiquidIO" in the subject.
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*
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* Copyright (c) 2003-2015 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium, Inc. for more information
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**********************************************************************/
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/*! \file octeon_main.h
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* \brief Host Driver: This file is included by all host driver source files
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* to include common definitions.
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*/
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#ifndef _OCTEON_MAIN_H_
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#define _OCTEON_MAIN_H_
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#if BITS_PER_LONG == 32
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#define CVM_CAST64(v) ((long long)(v))
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#elif BITS_PER_LONG == 64
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#define CVM_CAST64(v) ((long long)(long)(v))
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#else
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#error "Unknown system architecture"
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#endif
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#define DRV_NAME "LiquidIO"
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/**
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* \brief determines if a given console has debug enabled.
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* @param console console to check
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* @returns 1 = enabled. 0 otherwise
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*/
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int octeon_console_debug_enabled(u32 console);
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/* BQL-related functions */
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void octeon_report_sent_bytes_to_bql(void *buf, int reqtype);
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void octeon_update_tx_completion_counters(void *buf, int reqtype,
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unsigned int *pkts_compl,
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unsigned int *bytes_compl);
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void octeon_report_tx_completion_to_bql(void *txq, unsigned int pkts_compl,
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unsigned int bytes_compl);
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/** Swap 8B blocks */
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static inline void octeon_swap_8B_data(u64 *data, u32 blocks)
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{
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while (blocks) {
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cpu_to_be64s(data);
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blocks--;
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data++;
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}
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}
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/**
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* \brief unmaps a PCI BAR
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* @param oct Pointer to Octeon device
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* @param baridx bar index
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*/
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static inline void octeon_unmap_pci_barx(struct octeon_device *oct, int baridx)
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{
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dev_dbg(&oct->pci_dev->dev, "Freeing PCI mapped regions for Bar%d\n",
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baridx);
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if (oct->mmio[baridx].done)
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iounmap(oct->mmio[baridx].hw_addr);
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if (oct->mmio[baridx].start)
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pci_release_region(oct->pci_dev, baridx * 2);
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}
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/**
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* \brief maps a PCI BAR
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* @param oct Pointer to Octeon device
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* @param baridx bar index
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* @param max_map_len maximum length of mapped memory
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*/
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static inline int octeon_map_pci_barx(struct octeon_device *oct,
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int baridx, int max_map_len)
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{
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u32 mapped_len = 0;
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if (pci_request_region(oct->pci_dev, baridx * 2, DRV_NAME)) {
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dev_err(&oct->pci_dev->dev, "pci_request_region failed for bar %d\n",
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baridx);
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return 1;
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}
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oct->mmio[baridx].start = pci_resource_start(oct->pci_dev, baridx * 2);
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oct->mmio[baridx].len = pci_resource_len(oct->pci_dev, baridx * 2);
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mapped_len = oct->mmio[baridx].len;
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if (!mapped_len)
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return 1;
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if (max_map_len && (mapped_len > max_map_len))
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mapped_len = max_map_len;
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oct->mmio[baridx].hw_addr =
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ioremap(oct->mmio[baridx].start, mapped_len);
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oct->mmio[baridx].mapped_len = mapped_len;
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dev_dbg(&oct->pci_dev->dev, "BAR%d start: 0x%llx mapped %u of %u bytes\n",
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baridx, oct->mmio[baridx].start, mapped_len,
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oct->mmio[baridx].len);
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if (!oct->mmio[baridx].hw_addr) {
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dev_err(&oct->pci_dev->dev, "error ioremap for bar %d\n",
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baridx);
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return 1;
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}
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oct->mmio[baridx].done = 1;
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return 0;
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}
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static inline void *
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cnnic_numa_alloc_aligned_dma(u32 size,
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u32 *alloc_size,
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size_t *orig_ptr,
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int numa_node)
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{
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int retries = 0;
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void *ptr = NULL;
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#define OCTEON_MAX_ALLOC_RETRIES 1
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do {
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struct page *page = NULL;
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page = alloc_pages_node(numa_node,
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GFP_KERNEL,
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get_order(size));
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if (!page)
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page = alloc_pages(GFP_KERNEL,
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get_order(size));
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ptr = (void *)page_address(page);
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if ((unsigned long)ptr & 0x07) {
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__free_pages(page, get_order(size));
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ptr = NULL;
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/* Increment the size required if the first
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* attempt failed.
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*/
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if (!retries)
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size += 7;
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}
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retries++;
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} while ((retries <= OCTEON_MAX_ALLOC_RETRIES) && !ptr);
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*alloc_size = size;
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*orig_ptr = (unsigned long)ptr;
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if ((unsigned long)ptr & 0x07)
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ptr = (void *)(((unsigned long)ptr + 7) & ~(7UL));
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return ptr;
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}
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#define cnnic_free_aligned_dma(pci_dev, ptr, size, orig_ptr, dma_addr) \
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free_pages(orig_ptr, get_order(size))
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static inline void
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sleep_cond(wait_queue_head_t *wait_queue, int *condition)
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{
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wait_queue_t we;
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init_waitqueue_entry(&we, current);
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add_wait_queue(wait_queue, &we);
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while (!(ACCESS_ONCE(*condition))) {
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set_current_state(TASK_INTERRUPTIBLE);
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if (signal_pending(current))
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goto out;
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schedule();
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}
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out:
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set_current_state(TASK_RUNNING);
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remove_wait_queue(wait_queue, &we);
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}
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static inline void
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sleep_atomic_cond(wait_queue_head_t *waitq, atomic_t *pcond)
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{
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wait_queue_t we;
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init_waitqueue_entry(&we, current);
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add_wait_queue(waitq, &we);
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while (!atomic_read(pcond)) {
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set_current_state(TASK_INTERRUPTIBLE);
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if (signal_pending(current))
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goto out;
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schedule();
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}
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out:
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set_current_state(TASK_RUNNING);
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remove_wait_queue(waitq, &we);
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}
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/* Gives up the CPU for a timeout period.
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* Check that the condition is not true before we go to sleep for a
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* timeout period.
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*/
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static inline void
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sleep_timeout_cond(wait_queue_head_t *wait_queue,
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int *condition,
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int timeout)
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{
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wait_queue_t we;
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init_waitqueue_entry(&we, current);
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add_wait_queue(wait_queue, &we);
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set_current_state(TASK_INTERRUPTIBLE);
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if (!(*condition))
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schedule_timeout(timeout);
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set_current_state(TASK_RUNNING);
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remove_wait_queue(wait_queue, &we);
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}
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#ifndef ROUNDUP4
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#define ROUNDUP4(val) (((val) + 3) & 0xfffffffc)
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#endif
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#ifndef ROUNDUP8
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#define ROUNDUP8(val) (((val) + 7) & 0xfffffff8)
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#endif
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#ifndef ROUNDUP16
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#define ROUNDUP16(val) (((val) + 15) & 0xfffffff0)
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#endif
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#ifndef ROUNDUP128
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#define ROUNDUP128(val) (((val) + 127) & 0xffffff80)
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#endif
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#endif /* _OCTEON_MAIN_H_ */
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