mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-03 04:06:43 +07:00
bf35706f3d
This patch replaces the 'branch to setup()' instructions embedded in the PROCINFO structs with the offset to that setup function relative to the base of the struct. This preserves the position independent nature of that field, but uses a data item rather than an instruction. This is mainly done to prevent linker failures on large kernels, where the setup function is out of reach for the branch. Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
456 lines
12 KiB
ArmAsm
456 lines
12 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-mohawk.S: MMU functions for Marvell PJ1 core
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*
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* PJ1 (codename Mohawk) is a hybrid of the xscale3 and Marvell's own core.
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*
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* Heavily based on proc-arm926.S and proc-xsc3.S
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include "proc-macros.S"
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/*
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* This is the maximum size of an area which will be flushed. If the
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* area is larger than this, then we flush the whole cache.
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*/
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#define CACHE_DLIMIT 32768
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/*
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* The cache line size of the L1 D cache.
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*/
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#define CACHE_DLINESIZE 32
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/*
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* cpu_mohawk_proc_init()
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*/
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ENTRY(cpu_mohawk_proc_init)
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ret lr
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/*
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* cpu_mohawk_proc_fin()
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*/
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ENTRY(cpu_mohawk_proc_fin)
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1800 @ ...iz...........
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bic r0, r0, #0x0006 @ .............ca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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ret lr
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/*
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* cpu_mohawk_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* loc: location to jump to for soft reset
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*
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* (same as arm926)
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_mohawk_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x0007 @ .............cam
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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ret r0
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ENDPROC(cpu_mohawk_reset)
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.popsection
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/*
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* cpu_mohawk_do_idle()
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*
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* Called with IRQs disabled
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*/
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.align 5
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ENTRY(cpu_mohawk_do_idle)
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
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ret lr
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/*
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* flush_icache_all()
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*
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* Unconditionally clean and invalidate the entire icache.
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*/
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ENTRY(mohawk_flush_icache_all)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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ret lr
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ENDPROC(mohawk_flush_icache_all)
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/*
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* flush_user_cache_all()
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*
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* Clean and invalidate all cache entries in a particular
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* address space.
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*/
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ENTRY(mohawk_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(mohawk_flush_kern_cache_all)
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mov r2, #VM_EXEC
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mov ip, #0
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__flush_whole_cache:
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mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcrne p15, 0, ip, c7, c10, 0 @ drain write buffer
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ret lr
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* Clean and invalidate a range of cache entries in the
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* specified address range.
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*
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* - start - start address (inclusive)
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* - end - end address (exclusive)
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* - flags - vm_flags describing address space
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*
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* (same as arm926)
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*/
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ENTRY(mohawk_flush_user_cache_range)
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mov ip, #0
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sub r3, r1, r0 @ calculate total size
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cmp r3, #CACHE_DLIMIT
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bgt __flush_whole_cache
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1: tst r2, #VM_EXEC
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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ret lr
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(mohawk_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as arm926)
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*/
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ENTRY(mohawk_coherent_user_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov r0, #0
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ret lr
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/*
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* flush_kern_dcache_area(void *addr, size_t size)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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* - addr - kernel address
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* - size - region size
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*/
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ENTRY(mohawk_flush_kern_dcache_area)
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add r1, r0, r1
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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ret lr
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/*
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* dma_inv_range(start, end)
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*
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* Invalidate (discard) the specified virtual address range.
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* May not write back any entries. If 'start' or 'end'
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* are not cache line aligned, those lines must be written
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* back.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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mohawk_dma_inv_range:
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tst r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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tst r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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ret lr
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/*
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* dma_clean_range(start, end)
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*
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* Clean the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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mohawk_dma_clean_range:
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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ret lr
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/*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(mohawk_dma_flush_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1:
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mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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ret lr
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/*
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* dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(mohawk_dma_map_area)
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add r1, r1, r0
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cmp r2, #DMA_TO_DEVICE
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beq mohawk_dma_clean_range
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bcs mohawk_dma_inv_range
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b mohawk_dma_flush_range
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ENDPROC(mohawk_dma_map_area)
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/*
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* dma_unmap_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(mohawk_dma_unmap_area)
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ret lr
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ENDPROC(mohawk_dma_unmap_area)
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.globl mohawk_flush_kern_cache_louis
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.equ mohawk_flush_kern_cache_louis, mohawk_flush_kern_cache_all
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@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
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define_cache_functions mohawk
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ENTRY(cpu_mohawk_dcache_clean_area)
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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subs r1, r1, #CACHE_DLINESIZE
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bhi 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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ret lr
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/*
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* cpu_mohawk_switch_mm(pgd)
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*
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* Set the translation base pointer to be as described by pgd.
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*
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* pgd: new page tables
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*/
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.align 5
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ENTRY(cpu_mohawk_switch_mm)
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mov ip, #0
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mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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orr r0, r0, #0x18 @ cache the page table in L2
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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ret lr
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/*
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* cpu_mohawk_set_pte_ext(ptep, pte, ext)
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*
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* Set a PTE and flush it out
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*/
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.align 5
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ENTRY(cpu_mohawk_set_pte_ext)
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armv3_set_pte_ext
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mov r0, r0
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mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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ret lr
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.globl cpu_mohawk_suspend_size
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.equ cpu_mohawk_suspend_size, 4 * 6
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#ifdef CONFIG_ARM_CPU_SUSPEND
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ENTRY(cpu_mohawk_do_suspend)
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stmfd sp!, {r4 - r9, lr}
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mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
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mrc p15, 0, r5, c15, c1, 0 @ CP access reg
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mrc p15, 0, r6, c13, c0, 0 @ PID
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mrc p15, 0, r7, c3, c0, 0 @ domain ID
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mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
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mrc p15, 0, r9, c1, c0, 0 @ control reg
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bic r4, r4, #2 @ clear frequency change bit
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stmia r0, {r4 - r9} @ store cp regs
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ldmia sp!, {r4 - r9, pc}
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ENDPROC(cpu_mohawk_do_suspend)
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ENTRY(cpu_mohawk_do_resume)
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ldmia r0, {r4 - r9} @ load cp regs
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
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mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
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mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode.
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mcr p15, 0, r5, c15, c1, 0 @ CP access reg
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mcr p15, 0, r6, c13, c0, 0 @ PID
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mcr p15, 0, r7, c3, c0, 0 @ domain ID
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orr r1, r1, #0x18 @ cache the page table in L2
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mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
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mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
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mov r0, r9 @ control register
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b cpu_resume_mmu
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ENDPROC(cpu_mohawk_do_resume)
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#endif
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.type __mohawk_setup, #function
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__mohawk_setup:
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mov r0, #0
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mcr p15, 0, r0, c7, c7 @ invalidate I,D caches
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs
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orr r4, r4, #0x18 @ cache the page table in L2
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mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
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mov r0, #0 @ don't allow CP access
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mcr p15, 0, r0, c15, c1, 0 @ write CP access register
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adr r5, mohawk_crval
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ldmia r5, {r5, r6}
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mrc p15, 0, r0, c1, c0 @ get control register
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bic r0, r0, r5
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orr r0, r0, r6
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ret lr
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.size __mohawk_setup, . - __mohawk_setup
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/*
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* R
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* .RVI ZFRS BLDP WCAM
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* .011 1001 ..00 0101
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*
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*/
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.type mohawk_crval, #object
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mohawk_crval:
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crval clear=0x00007f3f, mmuset=0x00003905, ucset=0x00001134
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__INITDATA
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@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
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define_processor_functions mohawk, dabort=v5t_early_abort, pabort=legacy_pabort
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.section ".rodata"
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string cpu_arch_name, "armv5te"
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string cpu_elf_name, "v5"
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string cpu_mohawk_name, "Marvell 88SV331x"
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.align
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.section ".proc.info.init", #alloc
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.type __88sv331x_proc_info,#object
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__88sv331x_proc_info:
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.long 0x56158000 @ Marvell 88SV331x (MOHAWK)
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.long 0xfffff000
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.long PMD_TYPE_SECT | \
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PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | \
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PMD_BIT4 | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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.long PMD_TYPE_SECT | \
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PMD_BIT4 | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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initfn __mohawk_setup, __88sv331x_proc_info
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
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.long cpu_mohawk_name
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.long mohawk_processor_functions
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.long v4wbi_tlb_fns
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.long v4wb_user_fns
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.long mohawk_cache_fns
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.size __88sv331x_proc_info, . - __88sv331x_proc_info
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