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4c945e8556
Add support for the SolidRun Armada 388 Clearfog A1 board. This board has an Armada 388 microsom, dedicated gigabit ethernet, six switched gigabit ethernet ports, SFP cage, two Mini-PCIe/mSATA slots, a m.2 SATA slot, and a MikroBUS connector to allow MikroBUS modules to be added. This DT file adds support for all board facilities with the exception of full SFP support. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
116 lines
3.6 KiB
Plaintext
116 lines
3.6 KiB
Plaintext
/*
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* Device Tree file for SolidRun Armada 38x Microsom
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*
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* Copyright (C) 2015 Russell King
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*
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* This board is in development; the contents of this file work with
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* the A1 rev 2.0 of the board, which does not represent final
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* production board. Things will change, don't expect this file to
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* remain compatible info the future.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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memory {
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device_type = "memory";
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reg = <0x00000000 0x10000000>; /* 256 MB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
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internal-regs {
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ethernet@70000 {
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pinctrl-0 = <&ge0_rgmii_pins>;
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pinctrl-names = "default";
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phy = <&phy_dedicated>;
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phy-mode = "rgmii-id";
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status = "okay";
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};
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mdio@72004 {
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/*
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* Add the phy clock here, so the phy can be
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* accessed to read its IDs prior to binding
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* with the driver.
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*/
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pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>;
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pinctrl-names = "default";
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phy_dedicated: ethernet-phy@0 {
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/*
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* Annoyingly, the marvell phy driver
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* configures the LED register, rather
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* than preserving reset-loaded setting.
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* We undo that rubbish here.
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*/
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marvell,reg-init = <3 16 0 0x101e>;
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reg = <0>;
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};
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};
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pinctrl@18000 {
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microsom_phy_clk_pins: microsom-phy-clk-pins {
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marvell,pins = "mpp45";
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marvell,function = "ref";
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};
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};
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rtc@a3800 {
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/*
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* If the rtc doesn't work, run "date reset"
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* twice in u-boot.
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*/
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status = "okay";
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};
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serial@12000 {
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pinctrl-0 = <&uart0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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};
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};
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};
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