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The following 'capacity-dmips-mhz' dt property values are used: Cortex-A15: 1024, Cortex-A7: 539 They have been derived from the cpu_efficiency values: Cortex-A15: 3891, Cortex-A7: 2048 by scaling them so that the Cortex-A15s (big cores) use 1024. The cpu_efficiency values were originally derived from the "Big.LITTLE Processing with ARM Cortex™-A15 & Cortex-A7" white paper (http://www.cl.cam.ac.uk/~rdm34/big.LITTLE.pdf). Table 1 lists 1.9x (3891/2048) as the Cortex-A15 vs Cortex-A7 performance ratio for the Dhrystone benchmark. The following platforms are affected once cpu-invariant accounting support is re-connected to the task scheduler: arndale-octa, peach-pi, peach-pit, smdk5420 The patch has been tested on Samsung Chromebook 2 13" (peach-pi, Exynos 5800). $ cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 1024 1024 1024 389 389 389 389 The Cortex-A15 vs Cortex-A7 performance ratio is 1024/389 = 2.63. The values derived with the 'cpu_efficiency/clock-frequency dt property' solution are: $ cat /sys/devices/system/cpu/cpu*/cpu_capacity 1535 1535 1535 1535 448 448 448 448 The Cortex-A15 vs Cortex-A7 performance ratio is 1535/448 = 3.43. The discrepancy between 2.63 and 3.43 is due to the false assumption when using the 'cpu_efficiency/clock-frequency dt property' solution that the max cpu frequency of the little cpus is 1 GHZ and not 1.3 GHz. The Cortex-A7 cluster runs with a max cpu frequency of 1.3 GHZ whereas the 'clock-frequency' property value is set to 1 GHz. 3.43/1.3 = 2.64 $ cat /sys/devices/system/cpu/cpu*/cpufreq/scaling_max_freq 1800000 1800000 1800000 1800000 1300000 <-- max cpu frequency of the Cortex-A7s (little cores) 1300000 1300000 1300000 Running another benchmark (single-threaded sysbench affine to the individual cpus) with performance cpufreq governor on the Samsung Chromebook 2 13" showed the following numbers: $ for i in `seq 0 7`; do taskset -c $i sysbench --test=cpu --num-threads=1 --max-time=10 run | grep "total number of events:"; done total number of events: 1083 total number of events: 1085 total number of events: 1085 total number of events: 1085 total number of events: 454 total number of events: 454 total number of events: 454 total number of events: 454 The Cortex-A15 vs Cortex-A7 performance ratio is 2.39, i.e. very close to the one derived from the Dhrystone based one of the "Big.LITTLE Processing with ARM Cortex™-A15 & Cortex-A7" white paper (2.63). We don't aim for exact values for the cpu capacity values. Besides the CPI (Cycles Per Instruction), the instruction mix and whether the system runs cpu-bound or memory-bound has an impact on the cpu capacity values derived from these benchmark results. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
135 lines
3.8 KiB
Plaintext
135 lines
3.8 KiB
Plaintext
/*
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* SAMSUNG EXYNOS5420 SoC cpu device tree source
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*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This file provides desired ordering for Exynos5420 and Exynos5800
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* boards: CPU[0123] being the A15.
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*
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* The Exynos5420, 5422 and 5800 actually share the same CPU configuration
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* but particular boards choose different booting order.
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*
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* Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
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* booting cluster (big or LITTLE) is chosen by IROM code by reading
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* the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
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* from the LITTLE: Cortex-A7.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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clocks = <&clock CLK_ARM_CLK>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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operating-points-v2 = <&cluster_a15_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <11>;
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#cooling-cells = <2>; /* min followed by max */
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capacity-dmips-mhz = <1024>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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operating-points-v2 = <&cluster_a15_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <11>;
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#cooling-cells = <2>; /* min followed by max */
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capacity-dmips-mhz = <1024>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x2>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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operating-points-v2 = <&cluster_a15_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <11>;
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#cooling-cells = <2>; /* min followed by max */
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capacity-dmips-mhz = <1024>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x3>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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operating-points-v2 = <&cluster_a15_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <11>;
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#cooling-cells = <2>; /* min followed by max */
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capacity-dmips-mhz = <1024>;
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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clocks = <&clock CLK_KFC_CLK>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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operating-points-v2 = <&cluster_a7_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <7>;
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#cooling-cells = <2>; /* min followed by max */
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capacity-dmips-mhz = <539>;
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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operating-points-v2 = <&cluster_a7_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <7>;
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#cooling-cells = <2>; /* min followed by max */
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capacity-dmips-mhz = <539>;
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x102>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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operating-points-v2 = <&cluster_a7_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <7>;
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#cooling-cells = <2>; /* min followed by max */
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capacity-dmips-mhz = <539>;
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};
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cpu7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x103>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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operating-points-v2 = <&cluster_a7_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <7>;
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#cooling-cells = <2>; /* min followed by max */
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capacity-dmips-mhz = <539>;
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};
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};
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};
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