Xing Zheng 4608d96fb4 clk: rockchip: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src on rk3399 ... Sorry to refer incorrect clock diagram, we double check it that the bits configuration of the Xpll_aclk_perihp_src need to be fixed: bit 1 - shows aclk_perihp_cpll_src_en bit 0 - shows aclk_perihp_gpll_src_en Through the testing that plug/unplug the USB ethernet cable on the RK3399 kevin board. 1. the hclk_host0 and hclk_host1 are endpoint clocks: cpll --> G5[1] --> aclk_perihp_cpll_src --\ |--> hclk_host0 | --> ... ---> | gpll --> G5[0] --> aclk_perihp_gpll_src --/ |--> hclk_host1 2. there is no clock below the cpll_aclk_perihp_src, and the hclk_hostX are below the gpll_aclk_perihp_src: pll_cpll 1 1 800000000 0 0 cpll 7 19 800000000 0 0 cpll_aclk_perihp_src 0 0 800000000 0 0 ... pll_gpll 1 1 594000000 0 0 gpll 10 10 594000000 0 0 gpll_aclk_perihp_src 2 2 594000000 0 0 hclk_perihp 5 5 74250000 0 0 hclk_host1_arb 2 2 74250000 0 0 hclk_host1 2 2 74250000 0 0 hclk_host0_arb 2 2 74250000 0 0 hclk_host0 2 2 74250000 0 0 3. by default, G5[0] and G5[1] are enabled: localhost ~ # mem r 0xff760314 0x000003e0 4. close the G5[1] (aclk_perihp_cpll_src), and plug/unplug USB ethernet cable, the DUT still works well: localhost ~ # mem w 0xff760314 0xffff03e2 localhost ~ # mem r 0xff760314 0x000003e2 plug/unplug, the work statue is ok 5. close the G5[0] (aclk_perihp_gpll_src), , and plug/unplug USB ethernet cable, the DUT will be crashed: localhost ~ # mem w 0xff760314 0xffff03e1 localhost ~ # mem r 0xff760314 0x000003e1 plug/unplug, the DUT is crashed Summary: bit 1 - shows aclk_perihp_cpll_src_en bit 0 - shows aclk_perihp_gpll_src_en Fixes: 3bd14ae9da ("clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src") Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> [here the clock-documentation in the manual was actually stating the wrong bits and thus only Xing's testing above revealed the issue] Signed-off-by: Heiko Stuebner <heiko@sntech.de>		2016-08-12 18:09:19 +02:00
..
clk-cpu.c	clk: rockchip: fix cpuclk registration error handling	2016-05-30 09:40:23 +02:00
clk-inverter.c	clk: rockchip: don't return NULL when registering inverter fails	2016-02-15 23:35:20 +01:00
clk-mmc-phase.c	clk: rockchip: Revert "clk: rockchip: reset init state before mmc card initialization"	2016-05-30 09:40:23 +02:00
clk-pll.c	clk: rockchip: drop old_rate calculation on pll rate changes	2016-05-09 16:04:39 +02:00
clk-rk3036.c	clk: rockchip: release io resource when failing to init clk	2016-03-27 13:03:35 +02:00
clk-rk3188.c	clk: rockchip: release io resource when failing to init clk	2016-03-27 13:03:35 +02:00
clk-rk3228.c	clk: rockchip: export rk3228 MAC clocks	2016-07-01 01:50:11 +02:00
clk-rk3288.c	clk: rockchip: release io resource when failing to init clk	2016-03-27 13:03:35 +02:00
clk-rk3368.c	clk: rockchip: release io resource when failing to init clk	2016-03-27 13:03:35 +02:00
clk-rk3399.c	clk: rockchip: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src on rk3399	2016-08-12 18:09:19 +02:00
clk-rockchip.c	clk: rockchip: fix function type for CLK_OF_DECLARE	2014-05-20 14:25:22 -05:00
clk.c	clk: rockchip: simplify GRF handling in pll clocks	2016-05-09 16:04:15 +02:00
clk.h	clk: rockchip: simplify GRF handling in pll clocks	2016-05-09 16:04:15 +02:00
Makefile	clk: rockchip: add clock controller for the RK3399	2016-03-28 14:57:07 +02:00
softrst.c	clk: rockchip: Make reset_control_ops const	2016-03-29 16:29:46 -07:00