mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 00:47:11 +07:00
332 lines
8.2 KiB
C
332 lines
8.2 KiB
C
/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_bios.h"
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#include "nouveau_pm.h"
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static u32 read_clk(struct drm_device *, int, bool);
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static u32 read_pll(struct drm_device *, int, u32);
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static u32
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read_vco(struct drm_device *dev, int clk)
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{
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u32 sctl = nv_rd32(dev, 0x4120 + (clk * 4));
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if ((sctl & 0x00000030) != 0x00000030)
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return read_pll(dev, 0x41, 0x00e820);
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return read_pll(dev, 0x42, 0x00e8a0);
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}
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static u32
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read_clk(struct drm_device *dev, int clk, bool ignore_en)
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{
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u32 sctl, sdiv, sclk;
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/* refclk for the 0xe8xx plls always 27KHz */
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if (clk >= 0x40)
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return 27000;
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sctl = nv_rd32(dev, 0x4120 + (clk * 4));
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if (!ignore_en && !(sctl & 0x00000100))
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return 0;
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switch (sctl & 0x00003000) {
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case 0x00000000:
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return 27000;
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case 0x00002000:
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if (sctl & 0x00000040)
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return 108000;
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return 100000;
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case 0x00003000:
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sclk = read_vco(dev, clk);
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sdiv = ((sctl & 0x003f0000) >> 16) + 2;
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return (sclk * 2) / sdiv;
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default:
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return 0;
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}
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}
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static u32
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read_pll(struct drm_device *dev, int clk, u32 pll)
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{
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u32 ctrl = nv_rd32(dev, pll + 0);
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u32 sclk, P = 1, N = 1, M = 1;
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if (!(ctrl & 0x00000008)) {
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u32 coef = nv_rd32(dev, pll + 4);
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M = (coef & 0x000000ff) >> 0;
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N = (coef & 0x0000ff00) >> 8;
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P = (coef & 0x003f0000) >> 16;
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/* not post-divider on these.. */
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if ((pll & 0x00ff00) == 0x00e800)
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P = 1;
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sclk = read_clk(dev, 0x00 + clk, false);
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} else {
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sclk = read_clk(dev, 0x10 + clk, false);
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}
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return sclk * N / (M * P);
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}
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struct creg {
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u32 clk;
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u32 pll;
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};
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static int
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calc_clk(struct drm_device *dev, int clk, u32 pll, u32 khz, struct creg *reg)
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{
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struct pll_lims limits;
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u32 oclk, sclk, sdiv;
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int P, N, M, diff;
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int ret;
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reg->pll = 0;
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reg->clk = 0;
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if (!khz) {
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NV_DEBUG(dev, "no clock for 0x%04x/0x%02x\n", pll, clk);
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return 0;
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}
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switch (khz) {
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case 27000:
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reg->clk = 0x00000100;
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return khz;
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case 100000:
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reg->clk = 0x00002100;
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return khz;
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case 108000:
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reg->clk = 0x00002140;
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return khz;
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default:
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sclk = read_vco(dev, clk);
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sdiv = min((sclk * 2) / (khz - 2999), (u32)65);
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/* if the clock has a PLL attached, and we can get a within
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* [-2, 3) MHz of a divider, we'll disable the PLL and use
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* the divider instead.
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*
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* divider can go as low as 2, limited here because NVIDIA
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* and the VBIOS on my NVA8 seem to prefer using the PLL
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* for 810MHz - is there a good reason?
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*/
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if (sdiv > 4) {
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oclk = (sclk * 2) / sdiv;
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diff = khz - oclk;
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if (!pll || (diff >= -2000 && diff < 3000)) {
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reg->clk = (((sdiv - 2) << 16) | 0x00003100);
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return oclk;
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}
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}
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if (!pll) {
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NV_ERROR(dev, "bad freq %02x: %d %d\n", clk, khz, sclk);
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return -ERANGE;
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}
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break;
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}
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ret = get_pll_limits(dev, pll, &limits);
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if (ret)
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return ret;
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limits.refclk = read_clk(dev, clk - 0x10, true);
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if (!limits.refclk)
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return -EINVAL;
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ret = nva3_calc_pll(dev, &limits, khz, &N, NULL, &M, &P);
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if (ret >= 0) {
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reg->clk = nv_rd32(dev, 0x4120 + (clk * 4));
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reg->pll = (P << 16) | (N << 8) | M;
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}
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return ret;
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}
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static void
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prog_pll(struct drm_device *dev, int clk, u32 pll, struct creg *reg)
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{
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const u32 src0 = 0x004120 + (clk * 4);
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const u32 src1 = 0x004160 + (clk * 4);
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const u32 ctrl = pll + 0;
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const u32 coef = pll + 4;
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u32 cntl;
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if (!reg->clk && !reg->pll) {
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NV_DEBUG(dev, "no clock for %02x\n", clk);
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return;
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}
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cntl = nv_rd32(dev, ctrl) & 0xfffffff2;
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if (reg->pll) {
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nv_mask(dev, src0, 0x00000101, 0x00000101);
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nv_wr32(dev, coef, reg->pll);
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nv_wr32(dev, ctrl, cntl | 0x00000015);
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nv_mask(dev, src1, 0x00000100, 0x00000000);
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nv_mask(dev, src1, 0x00000001, 0x00000000);
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} else {
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nv_mask(dev, src1, 0x003f3141, 0x00000101 | reg->clk);
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nv_wr32(dev, ctrl, cntl | 0x0000001d);
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nv_mask(dev, ctrl, 0x00000001, 0x00000000);
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nv_mask(dev, src0, 0x00000100, 0x00000000);
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nv_mask(dev, src0, 0x00000001, 0x00000000);
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}
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}
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static void
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prog_clk(struct drm_device *dev, int clk, struct creg *reg)
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{
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if (!reg->clk) {
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NV_DEBUG(dev, "no clock for %02x\n", clk);
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return;
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}
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nv_mask(dev, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | reg->clk);
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}
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int
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nva3_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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{
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perflvl->core = read_pll(dev, 0x00, 0x4200);
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perflvl->shader = read_pll(dev, 0x01, 0x4220);
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perflvl->memory = read_pll(dev, 0x02, 0x4000);
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perflvl->unka0 = read_clk(dev, 0x20, false);
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perflvl->vdec = read_clk(dev, 0x21, false);
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perflvl->daemon = read_clk(dev, 0x25, false);
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perflvl->copy = perflvl->core;
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return 0;
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}
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struct nva3_pm_state {
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struct creg nclk;
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struct creg sclk;
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struct creg mclk;
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struct creg vdec;
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struct creg unka0;
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};
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void *
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nva3_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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{
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struct nva3_pm_state *info;
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int ret;
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info = kzalloc(sizeof(*info), GFP_KERNEL);
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if (!info)
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return ERR_PTR(-ENOMEM);
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ret = calc_clk(dev, 0x10, 0x4200, perflvl->core, &info->nclk);
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if (ret < 0)
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goto out;
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ret = calc_clk(dev, 0x11, 0x4220, perflvl->shader, &info->sclk);
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if (ret < 0)
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goto out;
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ret = calc_clk(dev, 0x12, 0x4000, perflvl->memory, &info->mclk);
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if (ret < 0)
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goto out;
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ret = calc_clk(dev, 0x20, 0x0000, perflvl->unka0, &info->unka0);
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if (ret < 0)
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goto out;
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ret = calc_clk(dev, 0x21, 0x0000, perflvl->vdec, &info->vdec);
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if (ret < 0)
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goto out;
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out:
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if (ret < 0) {
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kfree(info);
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info = ERR_PTR(ret);
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}
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return info;
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}
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static bool
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nva3_pm_grcp_idle(void *data)
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{
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struct drm_device *dev = data;
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if (!(nv_rd32(dev, 0x400304) & 0x00000001))
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return true;
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if (nv_rd32(dev, 0x400308) == 0x0050001c)
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return true;
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return false;
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}
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void
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nva3_pm_clocks_set(struct drm_device *dev, void *pre_state)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nva3_pm_state *info = pre_state;
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unsigned long flags;
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/* prevent any new grctx switches from starting */
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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nv_wr32(dev, 0x400324, 0x00000000);
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nv_wr32(dev, 0x400328, 0x0050001c); /* wait flag 0x1c */
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/* wait for any pending grctx switches to complete */
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if (!nv_wait_cb(dev, nva3_pm_grcp_idle, dev)) {
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NV_ERROR(dev, "pm: ctxprog didn't go idle\n");
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goto cleanup;
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}
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/* freeze PFIFO */
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nv_mask(dev, 0x002504, 0x00000001, 0x00000001);
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if (!nv_wait(dev, 0x002504, 0x00000010, 0x00000010)) {
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NV_ERROR(dev, "pm: fifo didn't go idle\n");
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goto cleanup;
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}
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prog_pll(dev, 0x00, 0x004200, &info->nclk);
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prog_pll(dev, 0x01, 0x004220, &info->sclk);
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prog_clk(dev, 0x20, &info->unka0);
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prog_clk(dev, 0x21, &info->vdec);
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nv_wr32(dev, 0x100210, 0);
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nv_wr32(dev, 0x1002dc, 1);
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nv_wr32(dev, 0x004018, 0x00001000);
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prog_pll(dev, 0x02, 0x004000, &info->mclk);
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if (nv_rd32(dev, 0x4000) & 0x00000008)
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nv_wr32(dev, 0x004018, 0x1000d000);
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else
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nv_wr32(dev, 0x004018, 0x10005000);
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nv_wr32(dev, 0x1002dc, 0);
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nv_wr32(dev, 0x100210, 0x80000000);
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cleanup:
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/* unfreeze PFIFO */
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nv_mask(dev, 0x002504, 0x00000001, 0x00000000);
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/* restore ctxprog to normal */
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nv_wr32(dev, 0x400324, 0x00000000);
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nv_wr32(dev, 0x400328, 0x0070009c); /* set flag 0x1c */
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/* unblock it if necessary */
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if (nv_rd32(dev, 0x400308) == 0x0050001c)
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nv_mask(dev, 0x400824, 0x10000000, 0x10000000);
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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kfree(info);
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}
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