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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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13569a709a
This patchset adds DT support for all the AXI, AHB, APB0 and APB1 gates present on sunxi SoCs. Signed-off-by: Emilio López <emilio@elopez.com.ar> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
152 lines
6.9 KiB
Plaintext
152 lines
6.9 KiB
Plaintext
Device Tree Clock bindings for arch-sunxi
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of the following:
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"allwinner,sun4i-osc-clk" - for a gatable oscillator
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"allwinner,sun4i-pll1-clk" - for the main PLL clock
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"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
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"allwinner,sun4i-axi-clk" - for the AXI clock
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"allwinner,sun4i-axi-gates-clk" - for the AXI gates
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"allwinner,sun4i-ahb-clk" - for the AHB clock
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"allwinner,sun4i-ahb-gates-clk" - for the AHB gates
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"allwinner,sun4i-apb0-clk" - for the APB0 clock
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"allwinner,sun4i-apb0-gates-clk" - for the APB0 gates
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"allwinner,sun4i-apb1-clk" - for the APB1 clock
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"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
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"allwinner,sun4i-apb1-gates-clk" - for the APB1 gates
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Required properties for all clocks:
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- reg : shall be the control register address for the clock.
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- clocks : shall be the input parent clock(s) phandle for the clock
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- #clock-cells : from common clock binding; shall be set to 0 except for
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"allwinner,sun4i-*-gates-clk" where it shall be set to 1
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Additionally, "allwinner,sun4i-*-gates-clk" clocks require:
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- clock-output-names : the corresponding gate names that the clock controls
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For example:
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osc24M: osc24M@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-osc-clk";
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reg = <0x01c20050 0x4>;
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clocks = <&osc24M_fixed>;
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};
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pll1: pll1@01c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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};
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-cpu-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>;
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};
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Gate clock outputs
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The "allwinner,sun4i-*-gates-clk" clocks provide several gatable outputs;
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their corresponding offsets as present on sun4i are listed below. Note that
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some of these gates are not present on sun5i.
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* AXI gates ("allwinner,sun4i-axi-gates-clk")
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DRAM 0
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* AHB gates ("allwinner,sun4i-ahb-gates-clk")
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USB0 0
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EHCI0 1
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OHCI0 2*
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EHCI1 3
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OHCI1 4*
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SS 5
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DMA 6
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BIST 7
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MMC0 8
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MMC1 9
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MMC2 10
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MMC3 11
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MS 12**
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NAND 13
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SDRAM 14
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ACE 16
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EMAC 17
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TS 18
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SPI0 20
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SPI1 21
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SPI2 22
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SPI3 23
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PATA 24
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SATA 25**
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GPS 26*
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VE 32
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TVD 33
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TVE0 34
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TVE1 35
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LCD0 36
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LCD1 37
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CSI0 40
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CSI1 41
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HDMI 43
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DE_BE0 44
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DE_BE1 45
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DE_FE0 46
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DE_FE1 47
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MP 50
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MALI400 52
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* APB0 gates ("allwinner,sun4i-apb0-gates-clk")
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CODEC 0
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SPDIF 1*
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AC97 2
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IIS 3
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PIO 5
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IR0 6
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IR1 7
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KEYPAD 10
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* APB1 gates ("allwinner,sun4i-apb1-gates-clk")
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I2C0 0
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I2C1 1
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I2C2 2
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CAN 4
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SCR 5
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PS20 6
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PS21 7
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UART0 16
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UART1 17
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UART2 18
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UART3 19
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UART4 20
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UART5 21
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UART6 22
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UART7 23
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Notation:
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[*]: The datasheet didn't mention these, but they are present on AW code
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[**]: The datasheet had this marked as "NC" but they are used on AW code
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