mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 19:25:46 +07:00
6e62bd36e9
drivers/soc/fsl/qe/gpio.c: In function qe_pin_request:
drivers/soc/fsl/qe/gpio.c:163:26: warning: variable mm_gc set but not used [-Wunused-but-set-variable]
commit 1e714e54b5
("powerpc: qe_lib-gpio: use gpiochip data pointer")
left behind this unused variable.
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Chen Zhou <chenzhou10@huawei.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
343 lines
8.4 KiB
C
343 lines
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* QUICC Engine GPIOs
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*
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* Copyright (c) MontaVista Software, Inc. 2008.
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*
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* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/gpio/driver.h>
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/* FIXME: needed for gpio_to_chip() get rid of this */
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <soc/fsl/qe/qe.h>
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struct qe_gpio_chip {
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struct of_mm_gpio_chip mm_gc;
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spinlock_t lock;
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unsigned long pin_flags[QE_PIO_PINS];
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#define QE_PIN_REQUESTED 0
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/* shadowed data register to clear/set bits safely */
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u32 cpdata;
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/* saved_regs used to restore dedicated functions */
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struct qe_pio_regs saved_regs;
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};
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static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
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{
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struct qe_gpio_chip *qe_gc =
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container_of(mm_gc, struct qe_gpio_chip, mm_gc);
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struct qe_pio_regs __iomem *regs = mm_gc->regs;
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qe_gc->cpdata = qe_ioread32be(®s->cpdata);
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qe_gc->saved_regs.cpdata = qe_gc->cpdata;
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qe_gc->saved_regs.cpdir1 = qe_ioread32be(®s->cpdir1);
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qe_gc->saved_regs.cpdir2 = qe_ioread32be(®s->cpdir2);
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qe_gc->saved_regs.cppar1 = qe_ioread32be(®s->cppar1);
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qe_gc->saved_regs.cppar2 = qe_ioread32be(®s->cppar2);
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qe_gc->saved_regs.cpodr = qe_ioread32be(®s->cpodr);
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}
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static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct qe_pio_regs __iomem *regs = mm_gc->regs;
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u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
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return !!(qe_ioread32be(®s->cpdata) & pin_mask);
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}
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static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
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struct qe_pio_regs __iomem *regs = mm_gc->regs;
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unsigned long flags;
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u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
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spin_lock_irqsave(&qe_gc->lock, flags);
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if (val)
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qe_gc->cpdata |= pin_mask;
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else
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qe_gc->cpdata &= ~pin_mask;
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qe_iowrite32be(qe_gc->cpdata, ®s->cpdata);
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spin_unlock_irqrestore(&qe_gc->lock, flags);
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}
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static void qe_gpio_set_multiple(struct gpio_chip *gc,
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unsigned long *mask, unsigned long *bits)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
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struct qe_pio_regs __iomem *regs = mm_gc->regs;
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unsigned long flags;
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int i;
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spin_lock_irqsave(&qe_gc->lock, flags);
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for (i = 0; i < gc->ngpio; i++) {
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if (*mask == 0)
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break;
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if (__test_and_clear_bit(i, mask)) {
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if (test_bit(i, bits))
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qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i));
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else
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qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i));
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}
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}
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qe_iowrite32be(qe_gc->cpdata, ®s->cpdata);
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spin_unlock_irqrestore(&qe_gc->lock, flags);
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}
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static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&qe_gc->lock, flags);
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__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
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spin_unlock_irqrestore(&qe_gc->lock, flags);
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return 0;
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}
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static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
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unsigned long flags;
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qe_gpio_set(gc, gpio, val);
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spin_lock_irqsave(&qe_gc->lock, flags);
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__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
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spin_unlock_irqrestore(&qe_gc->lock, flags);
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return 0;
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}
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struct qe_pin {
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/*
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* The qe_gpio_chip name is unfortunate, we should change that to
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* something like qe_pio_controller. Someday.
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*/
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struct qe_gpio_chip *controller;
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int num;
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};
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/**
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* qe_pin_request - Request a QE pin
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* @np: device node to get a pin from
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* @index: index of a pin in the device tree
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* Context: non-atomic
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*
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* This function return qe_pin so that you could use it with the rest of
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* the QE Pin Multiplexing API.
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*/
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struct qe_pin *qe_pin_request(struct device_node *np, int index)
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{
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struct qe_pin *qe_pin;
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struct gpio_chip *gc;
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struct qe_gpio_chip *qe_gc;
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int err;
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unsigned long flags;
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qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
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if (!qe_pin) {
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pr_debug("%s: can't allocate memory\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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err = of_get_gpio(np, index);
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if (err < 0)
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goto err0;
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gc = gpio_to_chip(err);
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if (WARN_ON(!gc)) {
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err = -ENODEV;
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goto err0;
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}
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if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) {
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pr_debug("%s: tried to get a non-qe pin\n", __func__);
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err = -EINVAL;
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goto err0;
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}
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qe_gc = gpiochip_get_data(gc);
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spin_lock_irqsave(&qe_gc->lock, flags);
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err -= gc->base;
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if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
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qe_pin->controller = qe_gc;
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qe_pin->num = err;
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err = 0;
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} else {
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err = -EBUSY;
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}
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spin_unlock_irqrestore(&qe_gc->lock, flags);
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if (!err)
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return qe_pin;
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err0:
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kfree(qe_pin);
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pr_debug("%s failed with status %d\n", __func__, err);
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return ERR_PTR(err);
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}
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EXPORT_SYMBOL(qe_pin_request);
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/**
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* qe_pin_free - Free a pin
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* @qe_pin: pointer to the qe_pin structure
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* Context: any
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*
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* This function frees the qe_pin structure and makes a pin available
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* for further qe_pin_request() calls.
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*/
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void qe_pin_free(struct qe_pin *qe_pin)
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{
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struct qe_gpio_chip *qe_gc = qe_pin->controller;
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unsigned long flags;
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const int pin = qe_pin->num;
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spin_lock_irqsave(&qe_gc->lock, flags);
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test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
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spin_unlock_irqrestore(&qe_gc->lock, flags);
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kfree(qe_pin);
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}
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EXPORT_SYMBOL(qe_pin_free);
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/**
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* qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
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* @qe_pin: pointer to the qe_pin structure
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* Context: any
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*
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* This function resets a pin to a dedicated peripheral function that
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* has been set up by the firmware.
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*/
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void qe_pin_set_dedicated(struct qe_pin *qe_pin)
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{
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struct qe_gpio_chip *qe_gc = qe_pin->controller;
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struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
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struct qe_pio_regs *sregs = &qe_gc->saved_regs;
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int pin = qe_pin->num;
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u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
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u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
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bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
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unsigned long flags;
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spin_lock_irqsave(&qe_gc->lock, flags);
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if (second_reg) {
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qe_clrsetbits_be32(®s->cpdir2, mask2,
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sregs->cpdir2 & mask2);
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qe_clrsetbits_be32(®s->cppar2, mask2,
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sregs->cppar2 & mask2);
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} else {
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qe_clrsetbits_be32(®s->cpdir1, mask2,
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sregs->cpdir1 & mask2);
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qe_clrsetbits_be32(®s->cppar1, mask2,
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sregs->cppar1 & mask2);
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}
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if (sregs->cpdata & mask1)
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qe_gc->cpdata |= mask1;
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else
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qe_gc->cpdata &= ~mask1;
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qe_iowrite32be(qe_gc->cpdata, ®s->cpdata);
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qe_clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1);
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spin_unlock_irqrestore(&qe_gc->lock, flags);
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}
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EXPORT_SYMBOL(qe_pin_set_dedicated);
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/**
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* qe_pin_set_gpio - Set a pin to the GPIO mode
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* @qe_pin: pointer to the qe_pin structure
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* Context: any
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*
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* This function sets a pin to the GPIO mode.
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*/
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void qe_pin_set_gpio(struct qe_pin *qe_pin)
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{
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struct qe_gpio_chip *qe_gc = qe_pin->controller;
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struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
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unsigned long flags;
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spin_lock_irqsave(&qe_gc->lock, flags);
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/* Let's make it input by default, GPIO API is able to change that. */
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__par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
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spin_unlock_irqrestore(&qe_gc->lock, flags);
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}
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EXPORT_SYMBOL(qe_pin_set_gpio);
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static int __init qe_add_gpiochips(void)
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{
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struct device_node *np;
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for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
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int ret;
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struct qe_gpio_chip *qe_gc;
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struct of_mm_gpio_chip *mm_gc;
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struct gpio_chip *gc;
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qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
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if (!qe_gc) {
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ret = -ENOMEM;
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goto err;
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}
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spin_lock_init(&qe_gc->lock);
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mm_gc = &qe_gc->mm_gc;
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gc = &mm_gc->gc;
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mm_gc->save_regs = qe_gpio_save_regs;
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gc->ngpio = QE_PIO_PINS;
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gc->direction_input = qe_gpio_dir_in;
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gc->direction_output = qe_gpio_dir_out;
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gc->get = qe_gpio_get;
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gc->set = qe_gpio_set;
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gc->set_multiple = qe_gpio_set_multiple;
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ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
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if (ret)
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goto err;
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continue;
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err:
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pr_err("%pOF: registration failed with status %d\n",
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np, ret);
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kfree(qe_gc);
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/* try others anyway */
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}
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return 0;
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}
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arch_initcall(qe_add_gpiochips);
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