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4ee93d80ad
On OpenRISC the icache does not snoop data stores. This can cause aliasing as reported by Jan. This patch fixes the issue to ensure icache is properly synchronized when code is written to memory. It supports both SMP and UP flushing. This supports dcache flush as well for architectures that do not support write-through caches; most OpenRISC implementations do implement write-through cache however. Dcache flushes are done only on a single core as OpenRISC dcaches all support snooping of bus stores. Signed-off-by: Jan Henrik Weinstock <jan.weinstock@ice.rwth-aachen.de> [shorne@gmail.com: Squashed patches and wrote commit message] Signed-off-by: Stafford Horne <shorne@gmail.com>
97 lines
3.4 KiB
C
97 lines
3.4 KiB
C
/*
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* OpenRISC Linux
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*
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* Linux architectural port borrowing liberally from similar works of
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* others. All original copyrights apply as per the original source
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* declaration.
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*
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* OpenRISC implementation:
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* Copyright (C) Jan Henrik Weinstock <jan.weinstock@rwth-aachen.de>
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* et al.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __ASM_CACHEFLUSH_H
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#define __ASM_CACHEFLUSH_H
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#include <linux/mm.h>
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/*
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* Helper function for flushing or invalidating entire pages from data
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* and instruction caches. SMP needs a little extra work, since we need
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* to flush the pages on all cpus.
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*/
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extern void local_dcache_page_flush(struct page *page);
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extern void local_icache_page_inv(struct page *page);
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/*
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* Data cache flushing always happen on the local cpu. Instruction cache
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* invalidations need to be broadcasted to all other cpu in the system in
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* case of SMP configurations.
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*/
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#ifndef CONFIG_SMP
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#define dcache_page_flush(page) local_dcache_page_flush(page)
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#define icache_page_inv(page) local_icache_page_inv(page)
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#else /* CONFIG_SMP */
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#define dcache_page_flush(page) local_dcache_page_flush(page)
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#define icache_page_inv(page) smp_icache_page_inv(page)
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extern void smp_icache_page_inv(struct page *page);
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#endif /* CONFIG_SMP */
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/*
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* Synchronizes caches. Whenever a cpu writes executable code to memory, this
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* should be called to make sure the processor sees the newly written code.
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*/
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static inline void sync_icache_dcache(struct page *page)
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{
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if (!IS_ENABLED(CONFIG_DCACHE_WRITETHROUGH))
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dcache_page_flush(page);
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icache_page_inv(page);
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}
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/*
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* Pages with this bit set need not be flushed/invalidated, since
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* they have not changed since last flush. New pages start with
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* PG_arch_1 not set and are therefore dirty by default.
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*/
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#define PG_dc_clean PG_arch_1
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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static inline void flush_dcache_page(struct page *page)
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{
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clear_bit(PG_dc_clean, &page->flags);
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}
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/*
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* Other interfaces are not required since we do not have virtually
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* indexed or tagged caches. So we can use the default here.
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*/
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define flush_icache_range(start, end) do { } while (0)
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#define flush_icache_page(vma, pg) do { } while (0)
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#define flush_icache_user_range(vma, pg, adr, len) do { } while (0)
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#define flush_cache_vmap(start, end) do { } while (0)
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#define flush_cache_vunmap(start, end) do { } while (0)
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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if (vma->vm_flags & VM_EXEC) \
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sync_icache_dcache(page); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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#endif /* __ASM_CACHEFLUSH_H */
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