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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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25985edced
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
729 lines
18 KiB
C
729 lines
18 KiB
C
/*
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* drivers/w1/masters/omap_hdq.c
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/sched.h>
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#include <asm/irq.h>
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#include <mach/hardware.h>
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#include "../w1.h"
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#include "../w1_int.h"
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#define MOD_NAME "OMAP_HDQ:"
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#define OMAP_HDQ_REVISION 0x00
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#define OMAP_HDQ_TX_DATA 0x04
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#define OMAP_HDQ_RX_DATA 0x08
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#define OMAP_HDQ_CTRL_STATUS 0x0c
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#define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK (1<<6)
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#define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE (1<<5)
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#define OMAP_HDQ_CTRL_STATUS_GO (1<<4)
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#define OMAP_HDQ_CTRL_STATUS_INITIALIZATION (1<<2)
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#define OMAP_HDQ_CTRL_STATUS_DIR (1<<1)
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#define OMAP_HDQ_CTRL_STATUS_MODE (1<<0)
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#define OMAP_HDQ_INT_STATUS 0x10
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#define OMAP_HDQ_INT_STATUS_TXCOMPLETE (1<<2)
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#define OMAP_HDQ_INT_STATUS_RXCOMPLETE (1<<1)
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#define OMAP_HDQ_INT_STATUS_TIMEOUT (1<<0)
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#define OMAP_HDQ_SYSCONFIG 0x14
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#define OMAP_HDQ_SYSCONFIG_SOFTRESET (1<<1)
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#define OMAP_HDQ_SYSCONFIG_AUTOIDLE (1<<0)
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#define OMAP_HDQ_SYSSTATUS 0x18
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#define OMAP_HDQ_SYSSTATUS_RESETDONE (1<<0)
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#define OMAP_HDQ_FLAG_CLEAR 0
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#define OMAP_HDQ_FLAG_SET 1
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#define OMAP_HDQ_TIMEOUT (HZ/5)
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#define OMAP_HDQ_MAX_USER 4
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static DECLARE_WAIT_QUEUE_HEAD(hdq_wait_queue);
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static int w1_id;
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struct hdq_data {
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struct device *dev;
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void __iomem *hdq_base;
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/* lock status update */
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struct mutex hdq_mutex;
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int hdq_usecount;
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struct clk *hdq_ick;
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struct clk *hdq_fck;
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u8 hdq_irqstatus;
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/* device lock */
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spinlock_t hdq_spinlock;
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/*
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* Used to control the call to omap_hdq_get and omap_hdq_put.
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* HDQ Protocol: Write the CMD|REG_address first, followed by
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* the data wrire or read.
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*/
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int init_trans;
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};
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static int __devinit omap_hdq_probe(struct platform_device *pdev);
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static int omap_hdq_remove(struct platform_device *pdev);
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static struct platform_driver omap_hdq_driver = {
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.probe = omap_hdq_probe,
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.remove = omap_hdq_remove,
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.driver = {
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.name = "omap_hdq",
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},
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};
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static u8 omap_w1_read_byte(void *_hdq);
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static void omap_w1_write_byte(void *_hdq, u8 byte);
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static u8 omap_w1_reset_bus(void *_hdq);
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static void omap_w1_search_bus(void *_hdq, struct w1_master *master_dev,
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u8 search_type, w1_slave_found_callback slave_found);
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static struct w1_bus_master omap_w1_master = {
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.read_byte = omap_w1_read_byte,
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.write_byte = omap_w1_write_byte,
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.reset_bus = omap_w1_reset_bus,
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.search = omap_w1_search_bus,
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};
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/* HDQ register I/O routines */
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static inline u8 hdq_reg_in(struct hdq_data *hdq_data, u32 offset)
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{
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return __raw_readb(hdq_data->hdq_base + offset);
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}
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static inline void hdq_reg_out(struct hdq_data *hdq_data, u32 offset, u8 val)
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{
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__raw_writeb(val, hdq_data->hdq_base + offset);
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}
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static inline u8 hdq_reg_merge(struct hdq_data *hdq_data, u32 offset,
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u8 val, u8 mask)
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{
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u8 new_val = (__raw_readb(hdq_data->hdq_base + offset) & ~mask)
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| (val & mask);
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__raw_writeb(new_val, hdq_data->hdq_base + offset);
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return new_val;
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}
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/*
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* Wait for one or more bits in flag change.
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* HDQ_FLAG_SET: wait until any bit in the flag is set.
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* HDQ_FLAG_CLEAR: wait until all bits in the flag are cleared.
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* return 0 on success and -ETIMEDOUT in the case of timeout.
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*/
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static int hdq_wait_for_flag(struct hdq_data *hdq_data, u32 offset,
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u8 flag, u8 flag_set, u8 *status)
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{
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int ret = 0;
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unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
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if (flag_set == OMAP_HDQ_FLAG_CLEAR) {
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/* wait for the flag clear */
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while (((*status = hdq_reg_in(hdq_data, offset)) & flag)
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&& time_before(jiffies, timeout)) {
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schedule_timeout_uninterruptible(1);
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}
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if (*status & flag)
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ret = -ETIMEDOUT;
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} else if (flag_set == OMAP_HDQ_FLAG_SET) {
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/* wait for the flag set */
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while (!((*status = hdq_reg_in(hdq_data, offset)) & flag)
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&& time_before(jiffies, timeout)) {
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schedule_timeout_uninterruptible(1);
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}
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if (!(*status & flag))
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ret = -ETIMEDOUT;
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} else
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return -EINVAL;
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return ret;
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}
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/* write out a byte and fill *status with HDQ_INT_STATUS */
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static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status)
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{
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int ret;
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u8 tmp_status;
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unsigned long irqflags;
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*status = 0;
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spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
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/* clear interrupt flags via a dummy read */
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hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
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/* ISR loads it with new INT_STATUS */
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hdq_data->hdq_irqstatus = 0;
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spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
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hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val);
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/* set the GO bit */
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hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO,
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OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
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/* wait for the TXCOMPLETE bit */
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ret = wait_event_timeout(hdq_wait_queue,
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hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
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if (ret == 0) {
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dev_dbg(hdq_data->dev, "TX wait elapsed\n");
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goto out;
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}
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*status = hdq_data->hdq_irqstatus;
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/* check irqstatus */
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if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) {
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dev_dbg(hdq_data->dev, "timeout waiting for"
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"TXCOMPLETE/RXCOMPLETE, %x", *status);
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ret = -ETIMEDOUT;
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goto out;
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}
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/* wait for the GO bit return to zero */
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ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
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OMAP_HDQ_CTRL_STATUS_GO,
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OMAP_HDQ_FLAG_CLEAR, &tmp_status);
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if (ret) {
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dev_dbg(hdq_data->dev, "timeout waiting GO bit"
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"return to zero, %x", tmp_status);
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}
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out:
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return ret;
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}
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/* HDQ Interrupt service routine */
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static irqreturn_t hdq_isr(int irq, void *_hdq)
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{
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struct hdq_data *hdq_data = _hdq;
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unsigned long irqflags;
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spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
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hdq_data->hdq_irqstatus = hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
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spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
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dev_dbg(hdq_data->dev, "hdq_isr: %x", hdq_data->hdq_irqstatus);
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if (hdq_data->hdq_irqstatus &
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(OMAP_HDQ_INT_STATUS_TXCOMPLETE | OMAP_HDQ_INT_STATUS_RXCOMPLETE
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| OMAP_HDQ_INT_STATUS_TIMEOUT)) {
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/* wake up sleeping process */
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wake_up(&hdq_wait_queue);
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}
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return IRQ_HANDLED;
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}
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/* HDQ Mode: always return success */
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static u8 omap_w1_reset_bus(void *_hdq)
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{
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return 0;
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}
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/* W1 search callback function */
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static void omap_w1_search_bus(void *_hdq, struct w1_master *master_dev,
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u8 search_type, w1_slave_found_callback slave_found)
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{
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u64 module_id, rn_le, cs, id;
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if (w1_id)
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module_id = w1_id;
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else
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module_id = 0x1;
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rn_le = cpu_to_le64(module_id);
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/*
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* HDQ might not obey truly the 1-wire spec.
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* So calculate CRC based on module parameter.
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*/
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cs = w1_calc_crc8((u8 *)&rn_le, 7);
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id = (cs << 56) | module_id;
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slave_found(master_dev, id);
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}
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static int _omap_hdq_reset(struct hdq_data *hdq_data)
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{
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int ret;
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u8 tmp_status;
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hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG, OMAP_HDQ_SYSCONFIG_SOFTRESET);
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/*
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* Select HDQ mode & enable clocks.
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* It is observed that INT flags can't be cleared via a read and GO/INIT
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* won't return to zero if interrupt is disabled. So we always enable
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* interrupt.
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*/
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hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
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OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
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OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
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/* wait for reset to complete */
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ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_SYSSTATUS,
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OMAP_HDQ_SYSSTATUS_RESETDONE, OMAP_HDQ_FLAG_SET, &tmp_status);
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if (ret)
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dev_dbg(hdq_data->dev, "timeout waiting HDQ reset, %x",
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tmp_status);
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else {
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hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
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OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
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OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
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hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
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OMAP_HDQ_SYSCONFIG_AUTOIDLE);
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}
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return ret;
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}
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/* Issue break pulse to the device */
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static int omap_hdq_break(struct hdq_data *hdq_data)
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{
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int ret = 0;
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u8 tmp_status;
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unsigned long irqflags;
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ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
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if (ret < 0) {
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dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
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ret = -EINTR;
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goto rtn;
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}
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spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
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/* clear interrupt flags via a dummy read */
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hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
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/* ISR loads it with new INT_STATUS */
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hdq_data->hdq_irqstatus = 0;
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spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
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/* set the INIT and GO bit */
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hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
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OMAP_HDQ_CTRL_STATUS_INITIALIZATION | OMAP_HDQ_CTRL_STATUS_GO,
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OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
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OMAP_HDQ_CTRL_STATUS_GO);
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/* wait for the TIMEOUT bit */
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ret = wait_event_timeout(hdq_wait_queue,
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hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
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if (ret == 0) {
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dev_dbg(hdq_data->dev, "break wait elapsed\n");
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ret = -EINTR;
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goto out;
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}
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tmp_status = hdq_data->hdq_irqstatus;
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/* check irqstatus */
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if (!(tmp_status & OMAP_HDQ_INT_STATUS_TIMEOUT)) {
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dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x",
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tmp_status);
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ret = -ETIMEDOUT;
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goto out;
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}
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/*
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* wait for both INIT and GO bits rerurn to zero.
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* zero wait time expected for interrupt mode.
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*/
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ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
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OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
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OMAP_HDQ_CTRL_STATUS_GO, OMAP_HDQ_FLAG_CLEAR,
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&tmp_status);
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if (ret)
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dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits"
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"return to zero, %x", tmp_status);
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out:
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mutex_unlock(&hdq_data->hdq_mutex);
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rtn:
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return ret;
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}
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static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val)
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{
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int ret = 0;
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u8 status;
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unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
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ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
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if (ret < 0) {
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ret = -EINTR;
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goto rtn;
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}
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if (!hdq_data->hdq_usecount) {
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ret = -EINVAL;
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goto out;
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}
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if (!(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
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hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
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OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO,
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OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
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/*
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* The RX comes immediately after TX. It
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* triggers another interrupt before we
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* sleep. So we have to wait for RXCOMPLETE bit.
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*/
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while (!(hdq_data->hdq_irqstatus
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& OMAP_HDQ_INT_STATUS_RXCOMPLETE)
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&& time_before(jiffies, timeout)) {
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schedule_timeout_uninterruptible(1);
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}
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hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0,
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OMAP_HDQ_CTRL_STATUS_DIR);
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status = hdq_data->hdq_irqstatus;
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/* check irqstatus */
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if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
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dev_dbg(hdq_data->dev, "timeout waiting for"
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"RXCOMPLETE, %x", status);
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ret = -ETIMEDOUT;
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goto out;
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}
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}
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/* the data is ready. Read it in! */
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*val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA);
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out:
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mutex_unlock(&hdq_data->hdq_mutex);
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rtn:
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return 0;
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}
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/* Enable clocks and set the controller to HDQ mode */
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static int omap_hdq_get(struct hdq_data *hdq_data)
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{
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int ret = 0;
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ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
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if (ret < 0) {
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ret = -EINTR;
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goto rtn;
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}
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if (OMAP_HDQ_MAX_USER == hdq_data->hdq_usecount) {
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dev_dbg(hdq_data->dev, "attempt to exceed the max use count");
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ret = -EINVAL;
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goto out;
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} else {
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hdq_data->hdq_usecount++;
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try_module_get(THIS_MODULE);
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if (1 == hdq_data->hdq_usecount) {
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if (clk_enable(hdq_data->hdq_ick)) {
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dev_dbg(hdq_data->dev, "Can not enable ick\n");
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ret = -ENODEV;
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goto clk_err;
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}
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if (clk_enable(hdq_data->hdq_fck)) {
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dev_dbg(hdq_data->dev, "Can not enable fck\n");
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clk_disable(hdq_data->hdq_ick);
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ret = -ENODEV;
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goto clk_err;
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}
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/* make sure HDQ is out of reset */
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if (!(hdq_reg_in(hdq_data, OMAP_HDQ_SYSSTATUS) &
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OMAP_HDQ_SYSSTATUS_RESETDONE)) {
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ret = _omap_hdq_reset(hdq_data);
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if (ret)
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/* back up the count */
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hdq_data->hdq_usecount--;
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} else {
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/* select HDQ mode & enable clocks */
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hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
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OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
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OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
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hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
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OMAP_HDQ_SYSCONFIG_AUTOIDLE);
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hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
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}
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}
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}
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clk_err:
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clk_put(hdq_data->hdq_ick);
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clk_put(hdq_data->hdq_fck);
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out:
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mutex_unlock(&hdq_data->hdq_mutex);
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rtn:
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return ret;
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}
|
|
|
|
/* Disable clocks to the module */
|
|
static int omap_hdq_put(struct hdq_data *hdq_data)
|
|
{
|
|
int ret = 0;
|
|
|
|
ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
|
|
if (ret < 0)
|
|
return -EINTR;
|
|
|
|
if (0 == hdq_data->hdq_usecount) {
|
|
dev_dbg(hdq_data->dev, "attempt to decrement use count"
|
|
"when it is zero");
|
|
ret = -EINVAL;
|
|
} else {
|
|
hdq_data->hdq_usecount--;
|
|
module_put(THIS_MODULE);
|
|
if (0 == hdq_data->hdq_usecount) {
|
|
clk_disable(hdq_data->hdq_ick);
|
|
clk_disable(hdq_data->hdq_fck);
|
|
}
|
|
}
|
|
mutex_unlock(&hdq_data->hdq_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* Read a byte of data from the device */
|
|
static u8 omap_w1_read_byte(void *_hdq)
|
|
{
|
|
struct hdq_data *hdq_data = _hdq;
|
|
u8 val = 0;
|
|
int ret;
|
|
|
|
ret = hdq_read_byte(hdq_data, &val);
|
|
if (ret) {
|
|
ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
|
|
if (ret < 0) {
|
|
dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
|
|
return -EINTR;
|
|
}
|
|
hdq_data->init_trans = 0;
|
|
mutex_unlock(&hdq_data->hdq_mutex);
|
|
omap_hdq_put(hdq_data);
|
|
return -1;
|
|
}
|
|
|
|
/* Write followed by a read, release the module */
|
|
if (hdq_data->init_trans) {
|
|
ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
|
|
if (ret < 0) {
|
|
dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
|
|
return -EINTR;
|
|
}
|
|
hdq_data->init_trans = 0;
|
|
mutex_unlock(&hdq_data->hdq_mutex);
|
|
omap_hdq_put(hdq_data);
|
|
}
|
|
|
|
return val;
|
|
}
|
|
|
|
/* Write a byte of data to the device */
|
|
static void omap_w1_write_byte(void *_hdq, u8 byte)
|
|
{
|
|
struct hdq_data *hdq_data = _hdq;
|
|
int ret;
|
|
u8 status;
|
|
|
|
/* First write to initialize the transfer */
|
|
if (hdq_data->init_trans == 0)
|
|
omap_hdq_get(hdq_data);
|
|
|
|
ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
|
|
if (ret < 0) {
|
|
dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
|
|
return;
|
|
}
|
|
hdq_data->init_trans++;
|
|
mutex_unlock(&hdq_data->hdq_mutex);
|
|
|
|
ret = hdq_write_byte(hdq_data, byte, &status);
|
|
if (ret == 0) {
|
|
dev_dbg(hdq_data->dev, "TX failure:Ctrl status %x\n", status);
|
|
return;
|
|
}
|
|
|
|
/* Second write, data transferred. Release the module */
|
|
if (hdq_data->init_trans > 1) {
|
|
omap_hdq_put(hdq_data);
|
|
ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
|
|
if (ret < 0) {
|
|
dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
|
|
return;
|
|
}
|
|
hdq_data->init_trans = 0;
|
|
mutex_unlock(&hdq_data->hdq_mutex);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
static int __devinit omap_hdq_probe(struct platform_device *pdev)
|
|
{
|
|
struct hdq_data *hdq_data;
|
|
struct resource *res;
|
|
int ret, irq;
|
|
u8 rev;
|
|
|
|
hdq_data = kmalloc(sizeof(*hdq_data), GFP_KERNEL);
|
|
if (!hdq_data) {
|
|
dev_dbg(&pdev->dev, "unable to allocate memory\n");
|
|
ret = -ENOMEM;
|
|
goto err_kmalloc;
|
|
}
|
|
|
|
hdq_data->dev = &pdev->dev;
|
|
platform_set_drvdata(pdev, hdq_data);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_dbg(&pdev->dev, "unable to get resource\n");
|
|
ret = -ENXIO;
|
|
goto err_resource;
|
|
}
|
|
|
|
hdq_data->hdq_base = ioremap(res->start, SZ_4K);
|
|
if (!hdq_data->hdq_base) {
|
|
dev_dbg(&pdev->dev, "ioremap failed\n");
|
|
ret = -EINVAL;
|
|
goto err_ioremap;
|
|
}
|
|
|
|
/* get interface & functional clock objects */
|
|
hdq_data->hdq_ick = clk_get(&pdev->dev, "ick");
|
|
if (IS_ERR(hdq_data->hdq_ick)) {
|
|
dev_dbg(&pdev->dev, "Can't get HDQ ick clock object\n");
|
|
ret = PTR_ERR(hdq_data->hdq_ick);
|
|
goto err_ick;
|
|
}
|
|
|
|
hdq_data->hdq_fck = clk_get(&pdev->dev, "fck");
|
|
if (IS_ERR(hdq_data->hdq_fck)) {
|
|
dev_dbg(&pdev->dev, "Can't get HDQ fck clock object\n");
|
|
ret = PTR_ERR(hdq_data->hdq_fck);
|
|
goto err_fck;
|
|
}
|
|
|
|
hdq_data->hdq_usecount = 0;
|
|
mutex_init(&hdq_data->hdq_mutex);
|
|
|
|
if (clk_enable(hdq_data->hdq_ick)) {
|
|
dev_dbg(&pdev->dev, "Can not enable ick\n");
|
|
ret = -ENODEV;
|
|
goto err_intfclk;
|
|
}
|
|
|
|
if (clk_enable(hdq_data->hdq_fck)) {
|
|
dev_dbg(&pdev->dev, "Can not enable fck\n");
|
|
ret = -ENODEV;
|
|
goto err_fnclk;
|
|
}
|
|
|
|
rev = hdq_reg_in(hdq_data, OMAP_HDQ_REVISION);
|
|
dev_info(&pdev->dev, "OMAP HDQ Hardware Rev %c.%c. Driver in %s mode\n",
|
|
(rev >> 4) + '0', (rev & 0x0f) + '0', "Interrupt");
|
|
|
|
spin_lock_init(&hdq_data->hdq_spinlock);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
ret = -ENXIO;
|
|
goto err_irq;
|
|
}
|
|
|
|
ret = request_irq(irq, hdq_isr, IRQF_DISABLED, "omap_hdq", hdq_data);
|
|
if (ret < 0) {
|
|
dev_dbg(&pdev->dev, "could not request irq\n");
|
|
goto err_irq;
|
|
}
|
|
|
|
omap_hdq_break(hdq_data);
|
|
|
|
/* don't clock the HDQ until it is needed */
|
|
clk_disable(hdq_data->hdq_ick);
|
|
clk_disable(hdq_data->hdq_fck);
|
|
|
|
omap_w1_master.data = hdq_data;
|
|
|
|
ret = w1_add_master_device(&omap_w1_master);
|
|
if (ret) {
|
|
dev_dbg(&pdev->dev, "Failure in registering w1 master\n");
|
|
goto err_w1;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_w1:
|
|
err_irq:
|
|
clk_disable(hdq_data->hdq_fck);
|
|
|
|
err_fnclk:
|
|
clk_disable(hdq_data->hdq_ick);
|
|
|
|
err_intfclk:
|
|
clk_put(hdq_data->hdq_fck);
|
|
|
|
err_fck:
|
|
clk_put(hdq_data->hdq_ick);
|
|
|
|
err_ick:
|
|
iounmap(hdq_data->hdq_base);
|
|
|
|
err_ioremap:
|
|
err_resource:
|
|
platform_set_drvdata(pdev, NULL);
|
|
kfree(hdq_data);
|
|
|
|
err_kmalloc:
|
|
return ret;
|
|
|
|
}
|
|
|
|
static int omap_hdq_remove(struct platform_device *pdev)
|
|
{
|
|
struct hdq_data *hdq_data = platform_get_drvdata(pdev);
|
|
|
|
mutex_lock(&hdq_data->hdq_mutex);
|
|
|
|
if (hdq_data->hdq_usecount) {
|
|
dev_dbg(&pdev->dev, "removed when use count is not zero\n");
|
|
mutex_unlock(&hdq_data->hdq_mutex);
|
|
return -EBUSY;
|
|
}
|
|
|
|
mutex_unlock(&hdq_data->hdq_mutex);
|
|
|
|
/* remove module dependency */
|
|
clk_put(hdq_data->hdq_ick);
|
|
clk_put(hdq_data->hdq_fck);
|
|
free_irq(INT_24XX_HDQ_IRQ, hdq_data);
|
|
platform_set_drvdata(pdev, NULL);
|
|
iounmap(hdq_data->hdq_base);
|
|
kfree(hdq_data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __init
|
|
omap_hdq_init(void)
|
|
{
|
|
return platform_driver_register(&omap_hdq_driver);
|
|
}
|
|
module_init(omap_hdq_init);
|
|
|
|
static void __exit
|
|
omap_hdq_exit(void)
|
|
{
|
|
platform_driver_unregister(&omap_hdq_driver);
|
|
}
|
|
module_exit(omap_hdq_exit);
|
|
|
|
module_param(w1_id, int, S_IRUSR);
|
|
MODULE_PARM_DESC(w1_id, "1-wire id for the slave detection");
|
|
|
|
MODULE_AUTHOR("Texas Instruments");
|
|
MODULE_DESCRIPTION("HDQ driver Library");
|
|
MODULE_LICENSE("GPL");
|