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69927fccd9
This patch adds the support for D_CAN controller driver to the existing C_CAN driver. Bosch D_CAN controller is a full-CAN implementation which is compliant to CAN protocol version 2.0 part A and B. Bosch D_CAN user manual can be obtained from: http://www.semiconductors.bosch.de/media/en/pdf/ ipmodules_1/can/d_can_users_manual_111.pdf A new array is added for accessing the d_can registers, according to d_can controller register space. Current D_CAN implementation has following limitations, this is done to avoid large changes to the C_CAN driver. 1. Message objects are limited to 32, 16 for RX and 16 for TX. C_CAN IP supports upto 32 message objects but in case of D_CAN we can configure upto 128 message objects. 2. Using two 16bit reads/writes for accessing the 32bit D_CAN registers. 3. These patches have been tested on little endian machine, there might be some hidden endian-related issues due to the nature of the accesses (32-bit registers accessed as 2 16-bit registers). However, I do not have a big-endian D_CAN implementation to confirm. Signed-off-by: AnilKumar Ch <anilkumar@ti.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
175 lines
4.6 KiB
C
175 lines
4.6 KiB
C
/*
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* CAN bus driver for Bosch C_CAN controller
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*
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* Copyright (C) 2010 ST Microelectronics
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* Bhupesh Sharma <bhupesh.sharma@st.com>
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*
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* Borrowed heavily from the C_CAN driver originally written by:
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* Copyright (C) 2007
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* - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
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* - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
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*
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* Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
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* Bosch C_CAN user manual can be obtained from:
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* http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
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* users_manual_c_can.pdf
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef C_CAN_H
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#define C_CAN_H
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enum reg {
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C_CAN_CTRL_REG = 0,
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C_CAN_STS_REG,
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C_CAN_ERR_CNT_REG,
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C_CAN_BTR_REG,
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C_CAN_INT_REG,
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C_CAN_TEST_REG,
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C_CAN_BRPEXT_REG,
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C_CAN_IF1_COMREQ_REG,
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C_CAN_IF1_COMMSK_REG,
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C_CAN_IF1_MASK1_REG,
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C_CAN_IF1_MASK2_REG,
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C_CAN_IF1_ARB1_REG,
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C_CAN_IF1_ARB2_REG,
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C_CAN_IF1_MSGCTRL_REG,
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C_CAN_IF1_DATA1_REG,
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C_CAN_IF1_DATA2_REG,
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C_CAN_IF1_DATA3_REG,
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C_CAN_IF1_DATA4_REG,
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C_CAN_IF2_COMREQ_REG,
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C_CAN_IF2_COMMSK_REG,
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C_CAN_IF2_MASK1_REG,
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C_CAN_IF2_MASK2_REG,
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C_CAN_IF2_ARB1_REG,
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C_CAN_IF2_ARB2_REG,
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C_CAN_IF2_MSGCTRL_REG,
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C_CAN_IF2_DATA1_REG,
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C_CAN_IF2_DATA2_REG,
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C_CAN_IF2_DATA3_REG,
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C_CAN_IF2_DATA4_REG,
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C_CAN_TXRQST1_REG,
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C_CAN_TXRQST2_REG,
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C_CAN_NEWDAT1_REG,
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C_CAN_NEWDAT2_REG,
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C_CAN_INTPND1_REG,
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C_CAN_INTPND2_REG,
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C_CAN_MSGVAL1_REG,
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C_CAN_MSGVAL2_REG,
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};
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static const u16 reg_map_c_can[] = {
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[C_CAN_CTRL_REG] = 0x00,
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[C_CAN_STS_REG] = 0x02,
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[C_CAN_ERR_CNT_REG] = 0x04,
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[C_CAN_BTR_REG] = 0x06,
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[C_CAN_INT_REG] = 0x08,
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[C_CAN_TEST_REG] = 0x0A,
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[C_CAN_BRPEXT_REG] = 0x0C,
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[C_CAN_IF1_COMREQ_REG] = 0x10,
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[C_CAN_IF1_COMMSK_REG] = 0x12,
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[C_CAN_IF1_MASK1_REG] = 0x14,
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[C_CAN_IF1_MASK2_REG] = 0x16,
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[C_CAN_IF1_ARB1_REG] = 0x18,
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[C_CAN_IF1_ARB2_REG] = 0x1A,
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[C_CAN_IF1_MSGCTRL_REG] = 0x1C,
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[C_CAN_IF1_DATA1_REG] = 0x1E,
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[C_CAN_IF1_DATA2_REG] = 0x20,
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[C_CAN_IF1_DATA3_REG] = 0x22,
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[C_CAN_IF1_DATA4_REG] = 0x24,
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[C_CAN_IF2_COMREQ_REG] = 0x40,
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[C_CAN_IF2_COMMSK_REG] = 0x42,
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[C_CAN_IF2_MASK1_REG] = 0x44,
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[C_CAN_IF2_MASK2_REG] = 0x46,
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[C_CAN_IF2_ARB1_REG] = 0x48,
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[C_CAN_IF2_ARB2_REG] = 0x4A,
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[C_CAN_IF2_MSGCTRL_REG] = 0x4C,
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[C_CAN_IF2_DATA1_REG] = 0x4E,
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[C_CAN_IF2_DATA2_REG] = 0x50,
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[C_CAN_IF2_DATA3_REG] = 0x52,
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[C_CAN_IF2_DATA4_REG] = 0x54,
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[C_CAN_TXRQST1_REG] = 0x80,
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[C_CAN_TXRQST2_REG] = 0x82,
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[C_CAN_NEWDAT1_REG] = 0x90,
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[C_CAN_NEWDAT2_REG] = 0x92,
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[C_CAN_INTPND1_REG] = 0xA0,
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[C_CAN_INTPND2_REG] = 0xA2,
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[C_CAN_MSGVAL1_REG] = 0xB0,
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[C_CAN_MSGVAL2_REG] = 0xB2,
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};
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static const u16 reg_map_d_can[] = {
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[C_CAN_CTRL_REG] = 0x00,
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[C_CAN_STS_REG] = 0x04,
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[C_CAN_ERR_CNT_REG] = 0x08,
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[C_CAN_BTR_REG] = 0x0C,
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[C_CAN_BRPEXT_REG] = 0x0E,
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[C_CAN_INT_REG] = 0x10,
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[C_CAN_TEST_REG] = 0x14,
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[C_CAN_TXRQST1_REG] = 0x88,
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[C_CAN_TXRQST2_REG] = 0x8A,
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[C_CAN_NEWDAT1_REG] = 0x9C,
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[C_CAN_NEWDAT2_REG] = 0x9E,
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[C_CAN_INTPND1_REG] = 0xB0,
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[C_CAN_INTPND2_REG] = 0xB2,
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[C_CAN_MSGVAL1_REG] = 0xC4,
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[C_CAN_MSGVAL2_REG] = 0xC6,
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[C_CAN_IF1_COMREQ_REG] = 0x100,
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[C_CAN_IF1_COMMSK_REG] = 0x102,
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[C_CAN_IF1_MASK1_REG] = 0x104,
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[C_CAN_IF1_MASK2_REG] = 0x106,
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[C_CAN_IF1_ARB1_REG] = 0x108,
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[C_CAN_IF1_ARB2_REG] = 0x10A,
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[C_CAN_IF1_MSGCTRL_REG] = 0x10C,
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[C_CAN_IF1_DATA1_REG] = 0x110,
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[C_CAN_IF1_DATA2_REG] = 0x112,
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[C_CAN_IF1_DATA3_REG] = 0x114,
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[C_CAN_IF1_DATA4_REG] = 0x116,
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[C_CAN_IF2_COMREQ_REG] = 0x120,
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[C_CAN_IF2_COMMSK_REG] = 0x122,
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[C_CAN_IF2_MASK1_REG] = 0x124,
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[C_CAN_IF2_MASK2_REG] = 0x126,
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[C_CAN_IF2_ARB1_REG] = 0x128,
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[C_CAN_IF2_ARB2_REG] = 0x12A,
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[C_CAN_IF2_MSGCTRL_REG] = 0x12C,
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[C_CAN_IF2_DATA1_REG] = 0x130,
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[C_CAN_IF2_DATA2_REG] = 0x132,
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[C_CAN_IF2_DATA3_REG] = 0x134,
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[C_CAN_IF2_DATA4_REG] = 0x136,
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};
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enum c_can_dev_id {
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C_CAN_DEVTYPE,
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D_CAN_DEVTYPE,
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};
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/* c_can private data structure */
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struct c_can_priv {
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struct can_priv can; /* must be the first member */
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struct napi_struct napi;
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struct net_device *dev;
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int tx_object;
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int current_status;
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int last_status;
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u16 (*read_reg) (struct c_can_priv *priv, enum reg index);
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void (*write_reg) (struct c_can_priv *priv, enum reg index, u16 val);
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void __iomem *base;
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const u16 *regs;
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unsigned long irq_flags; /* for request_irq() */
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unsigned int tx_next;
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unsigned int tx_echo;
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void *priv; /* for board-specific data */
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u16 irqstatus;
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};
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struct net_device *alloc_c_can_dev(void);
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void free_c_can_dev(struct net_device *dev);
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int register_c_can_dev(struct net_device *dev);
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void unregister_c_can_dev(struct net_device *dev);
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#endif /* C_CAN_H */
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