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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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74b48999b1
* clk-qcom-alpha-pll: clk: qcom: add read-only alpha pll post divider operations clk: qcom: support for 2 bit PLL post divider clk: qcom: support Brammo type Alpha PLL clk: qcom: support Huayra type Alpha PLL clk: qcom: support for dynamic updating the PLL clk: qcom: support for alpha mode configuration clk: qcom: flag for 64 bit CONFIG_CTL clk: qcom: fix 16 bit alpha support calculation clk: qcom: support for alpha pll properties * clk-check-ops-ptr: clk: check ops pointer on clock register * clk-protect-rate: clk: fix set_rate_range when current rate is out of range clk: add clk_rate_exclusive api clk: cosmetic changes to clk_summary debugfs entry clk: add clock protection mechanism to clk core clk: use round rate to bail out early in set_rate clk: rework calls to round and determine rate callbacks clk: add clk_core_set_phase_nolock function clk: take the prepare lock out of clk_core_set_parent clk: fix incorrect usage of ENOSYS * clk-omap: clk: ti: Drop legacy clk-3xxx-legacy code |
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.. | ||
adpll.c | ||
apll.c | ||
autoidle.c | ||
clk-2xxx.c | ||
clk-3xxx.c | ||
clk-7xx.c | ||
clk-33xx.c | ||
clk-43xx.c | ||
clk-44xx.c | ||
clk-54xx.c | ||
clk-814x.c | ||
clk-816x.c | ||
clk-dra7-atl.c | ||
clk.c | ||
clkctrl.c | ||
clkt_dflt.c | ||
clkt_dpll.c | ||
clkt_iclk.c | ||
clock.h | ||
clockdomain.c | ||
composite.c | ||
divider.c | ||
dpll3xxx.c | ||
dpll44xx.c | ||
dpll.c | ||
fapll.c | ||
fixed-factor.c | ||
gate.c | ||
interface.c | ||
Kconfig | ||
Makefile | ||
mux.c |