Marc Zyngier 96806229ca irqchip/gic-v4.1: Add support for VPENDBASER's Dirty+Valid signaling ... When a vPE is made resident, the GIC starts parsing the virtual pending table to deliver pending interrupts. This takes place asynchronously, and can at times take a long while. Long enough that the vcpu enters the guest and hits WFI before any interrupt has been signaled yet. The vcpu then exits, blocks, and now gets a doorbell. Rince, repeat. In order to avoid the above, a (optional on GICv4, mandatory on v4.1) feature allows the GIC to feedback to the hypervisor whether it is done parsing the VPT by clearing the GICR_VPENDBASER.Dirty bit. The hypervisor can then wait until the GIC is ready before actually running the vPE. Plug the detection code as well as polling on vPE schedule. While at it, tidy-up the kernel message that displays the GICv4 optional features. Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org>		2020-04-16 10:28:12 +01:00
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arm-gic-common.h	irqchip/gic-v4.1: Advertise support v4.1 to KVM	2020-03-20 17:48:38 +00:00
arm-gic-v3.h	irqchip/gic-v4.1: Add support for VPENDBASER's Dirty+Valid signaling	2020-04-16 10:28:12 +01:00
arm-gic-v4.h	irqchip/gic-v4.1: Add VSGI property setup	2020-03-24 12:15:51 +00:00
arm-gic.h	Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip	2019-07-08 11:01:13 -07:00
arm-vic.h
chained_irq.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234	2019-06-19 17:09:07 +02:00
irq-bcm2836.h
irq-davinci-aintc.h
irq-davinci-cp-intc.h
irq-ixp4xx.h
irq-madera.h
irq-omap-intc.h
irq-partition-percpu.h	irqchip: Add include guard to irq-partition-percpu.h	2019-08-20 10:35:46 +01:00
irq-sa11x0.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
mmp.h
mxs.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
versatile-fpga.h
xtensa-mx.h
xtensa-pic.h