Joseph Lo 0ac65fc946 clk: tegra: Implement Tegra210 EMC clock ... The EMC clock needs to carefully coordinate with the EMC controller programming to make sure external memory can be properly clocked. Do so by hooking up the EMC clock with an EMC provider that will specify which rates are supported by the EMC and provide a callback to use for setting the clock rate at the EMC. Based on work by Peter De Schrijver <pdeschrijver@nvidia.com>. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>		2020-05-12 22:48:42 +02:00
..
analogbits-wrpll-cln28hpc.h	clk: analogbits: add Wide-Range PLL library	2019-05-03 09:20:48 -07:00
at91_pmc.h	clk: at91: move sam9x60's PLL register offsets to PMC header	2020-02-18 21:47:54 +01:00
clk-conf.h	clk: add include guard to clk-conf.h	2019-09-17 10:27:46 -07:00
davinci.h	clk: davinci: Fix link errors when not all SoCs are enabled	2018-05-30 12:48:49 -07:00
mmp.h	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
mxs.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
renesas.h	clk: renesas: Convert to SPDX identifiers	2018-09-28 17:16:37 -07:00
sunxi-ng.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282	2019-06-05 17:36:37 +02:00
tegra.h	clk: tegra: Implement Tegra210 EMC clock	2020-05-12 22:48:42 +02:00
ti.h	clk: ti: clkctrl: add new exported API for checking standby info	2019-10-31 15:18:28 +02:00
zynq.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 156	2019-05-30 11:26:35 -07:00