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2a0fe914a3
SDIO_CCCR_IF[1:0] in SDIO card is used for card data bus width
setting as below:
00b: 1-bit bus
01b: Reserved
10b: 4-bit bus
11b: 8-bit bus (only for embedded SDIO)
And sdio_enable_wide is for setting data bus width as 4-bit.
But currently, it first reads the register, second OR' 1b with
SDIO_CCCR_IF[1], and then writes it back.
As we can see, this is based on such assumption that the
SDIO_CCCR_IF[0] is always 0. Apparently, this is not right.
Signed-off-by: Yong Ding <yongd@marvell.com>
Acked-by: Philip Rakity <prakity@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
194 lines
6.2 KiB
C
194 lines
6.2 KiB
C
/*
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* include/linux/mmc/sdio.h
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*
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* Copyright 2006-2007 Pierre Ossman
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#ifndef LINUX_MMC_SDIO_H
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#define LINUX_MMC_SDIO_H
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/* SDIO commands type argument response */
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#define SD_IO_SEND_OP_COND 5 /* bcr [23:0] OCR R4 */
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#define SD_IO_RW_DIRECT 52 /* ac [31:0] See below R5 */
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#define SD_IO_RW_EXTENDED 53 /* adtc [31:0] See below R5 */
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/*
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* SD_IO_RW_DIRECT argument format:
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*
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* [31] R/W flag
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* [30:28] Function number
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* [27] RAW flag
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* [25:9] Register address
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* [7:0] Data
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*/
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/*
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* SD_IO_RW_EXTENDED argument format:
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*
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* [31] R/W flag
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* [30:28] Function number
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* [27] Block mode
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* [26] Increment address
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* [25:9] Register address
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* [8:0] Byte/block count
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*/
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#define R4_18V_PRESENT (1<<24)
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#define R4_MEMORY_PRESENT (1 << 27)
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/*
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SDIO status in R5
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Type
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e : error bit
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s : status bit
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r : detected and set for the actual command response
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x : detected and set during command execution. the host must poll
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the card by sending status command in order to read these bits.
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Clear condition
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a : according to the card state
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b : always related to the previous command. Reception of
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a valid command will clear it (with a delay of one command)
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c : clear by read
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*/
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#define R5_COM_CRC_ERROR (1 << 15) /* er, b */
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#define R5_ILLEGAL_COMMAND (1 << 14) /* er, b */
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#define R5_ERROR (1 << 11) /* erx, c */
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#define R5_FUNCTION_NUMBER (1 << 9) /* er, c */
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#define R5_OUT_OF_RANGE (1 << 8) /* er, c */
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#define R5_STATUS(x) (x & 0xCB00)
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#define R5_IO_CURRENT_STATE(x) ((x & 0x3000) >> 12) /* s, b */
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/*
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* Card Common Control Registers (CCCR)
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*/
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#define SDIO_CCCR_CCCR 0x00
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#define SDIO_CCCR_REV_1_00 0 /* CCCR/FBR Version 1.00 */
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#define SDIO_CCCR_REV_1_10 1 /* CCCR/FBR Version 1.10 */
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#define SDIO_CCCR_REV_1_20 2 /* CCCR/FBR Version 1.20 */
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#define SDIO_CCCR_REV_3_00 3 /* CCCR/FBR Version 3.00 */
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#define SDIO_SDIO_REV_1_00 0 /* SDIO Spec Version 1.00 */
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#define SDIO_SDIO_REV_1_10 1 /* SDIO Spec Version 1.10 */
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#define SDIO_SDIO_REV_1_20 2 /* SDIO Spec Version 1.20 */
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#define SDIO_SDIO_REV_2_00 3 /* SDIO Spec Version 2.00 */
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#define SDIO_SDIO_REV_3_00 4 /* SDIO Spec Version 3.00 */
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#define SDIO_CCCR_SD 0x01
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#define SDIO_SD_REV_1_01 0 /* SD Physical Spec Version 1.01 */
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#define SDIO_SD_REV_1_10 1 /* SD Physical Spec Version 1.10 */
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#define SDIO_SD_REV_2_00 2 /* SD Physical Spec Version 2.00 */
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#define SDIO_SD_REV_3_00 3 /* SD Physical Spev Version 3.00 */
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#define SDIO_CCCR_IOEx 0x02
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#define SDIO_CCCR_IORx 0x03
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#define SDIO_CCCR_IENx 0x04 /* Function/Master Interrupt Enable */
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#define SDIO_CCCR_INTx 0x05 /* Function Interrupt Pending */
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#define SDIO_CCCR_ABORT 0x06 /* function abort/card reset */
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#define SDIO_CCCR_IF 0x07 /* bus interface controls */
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#define SDIO_BUS_WIDTH_MASK 0x03 /* data bus width setting */
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#define SDIO_BUS_WIDTH_1BIT 0x00
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#define SDIO_BUS_WIDTH_RESERVED 0x01
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#define SDIO_BUS_WIDTH_4BIT 0x02
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#define SDIO_BUS_ECSI 0x20 /* Enable continuous SPI interrupt */
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#define SDIO_BUS_SCSI 0x40 /* Support continuous SPI interrupt */
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#define SDIO_BUS_ASYNC_INT 0x20
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#define SDIO_BUS_CD_DISABLE 0x80 /* disable pull-up on DAT3 (pin 1) */
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#define SDIO_CCCR_CAPS 0x08
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#define SDIO_CCCR_CAP_SDC 0x01 /* can do CMD52 while data transfer */
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#define SDIO_CCCR_CAP_SMB 0x02 /* can do multi-block xfers (CMD53) */
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#define SDIO_CCCR_CAP_SRW 0x04 /* supports read-wait protocol */
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#define SDIO_CCCR_CAP_SBS 0x08 /* supports suspend/resume */
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#define SDIO_CCCR_CAP_S4MI 0x10 /* interrupt during 4-bit CMD53 */
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#define SDIO_CCCR_CAP_E4MI 0x20 /* enable ints during 4-bit CMD53 */
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#define SDIO_CCCR_CAP_LSC 0x40 /* low speed card */
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#define SDIO_CCCR_CAP_4BLS 0x80 /* 4 bit low speed card */
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#define SDIO_CCCR_CIS 0x09 /* common CIS pointer (3 bytes) */
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/* Following 4 regs are valid only if SBS is set */
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#define SDIO_CCCR_SUSPEND 0x0c
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#define SDIO_CCCR_SELx 0x0d
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#define SDIO_CCCR_EXECx 0x0e
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#define SDIO_CCCR_READYx 0x0f
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#define SDIO_CCCR_BLKSIZE 0x10
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#define SDIO_CCCR_POWER 0x12
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#define SDIO_POWER_SMPC 0x01 /* Supports Master Power Control */
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#define SDIO_POWER_EMPC 0x02 /* Enable Master Power Control */
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#define SDIO_CCCR_SPEED 0x13
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#define SDIO_SPEED_SHS 0x01 /* Supports High-Speed mode */
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#define SDIO_SPEED_BSS_SHIFT 1
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#define SDIO_SPEED_BSS_MASK (7<<SDIO_SPEED_BSS_SHIFT)
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#define SDIO_SPEED_SDR12 (0<<SDIO_SPEED_BSS_SHIFT)
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#define SDIO_SPEED_SDR25 (1<<SDIO_SPEED_BSS_SHIFT)
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#define SDIO_SPEED_SDR50 (2<<SDIO_SPEED_BSS_SHIFT)
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#define SDIO_SPEED_SDR104 (3<<SDIO_SPEED_BSS_SHIFT)
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#define SDIO_SPEED_DDR50 (4<<SDIO_SPEED_BSS_SHIFT)
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#define SDIO_SPEED_EHS SDIO_SPEED_SDR25 /* Enable High-Speed */
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#define SDIO_CCCR_UHS 0x14
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#define SDIO_UHS_SDR50 0x01
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#define SDIO_UHS_SDR104 0x02
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#define SDIO_UHS_DDR50 0x04
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#define SDIO_CCCR_DRIVE_STRENGTH 0x15
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#define SDIO_SDTx_MASK 0x07
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#define SDIO_DRIVE_SDTA (1<<0)
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#define SDIO_DRIVE_SDTC (1<<1)
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#define SDIO_DRIVE_SDTD (1<<2)
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#define SDIO_DRIVE_DTSx_MASK 0x03
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#define SDIO_DRIVE_DTSx_SHIFT 4
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#define SDIO_DTSx_SET_TYPE_B (0 << SDIO_DRIVE_DTSx_SHIFT)
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#define SDIO_DTSx_SET_TYPE_A (1 << SDIO_DRIVE_DTSx_SHIFT)
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#define SDIO_DTSx_SET_TYPE_C (2 << SDIO_DRIVE_DTSx_SHIFT)
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#define SDIO_DTSx_SET_TYPE_D (3 << SDIO_DRIVE_DTSx_SHIFT)
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/*
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* Function Basic Registers (FBR)
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*/
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#define SDIO_FBR_BASE(f) ((f) * 0x100) /* base of function f's FBRs */
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#define SDIO_FBR_STD_IF 0x00
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#define SDIO_FBR_SUPPORTS_CSA 0x40 /* supports Code Storage Area */
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#define SDIO_FBR_ENABLE_CSA 0x80 /* enable Code Storage Area */
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#define SDIO_FBR_STD_IF_EXT 0x01
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#define SDIO_FBR_POWER 0x02
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#define SDIO_FBR_POWER_SPS 0x01 /* Supports Power Selection */
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#define SDIO_FBR_POWER_EPS 0x02 /* Enable (low) Power Selection */
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#define SDIO_FBR_CIS 0x09 /* CIS pointer (3 bytes) */
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#define SDIO_FBR_CSA 0x0C /* CSA pointer (3 bytes) */
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#define SDIO_FBR_CSA_DATA 0x0F
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#define SDIO_FBR_BLKSIZE 0x10 /* block size (2 bytes) */
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#endif /* LINUX_MMC_SDIO_H */
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