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449ef7f6a9
Host map configuration instructs the interrupt controller to route interrupt channels to FIQ or IRQ lines. Currently, DA8xx family of devices leave these registers at their reset-default values. TNETV107X however does not have sane reset defaults, and therefore this architecture needs to reconfigure the host-map such that channels 0 and 1 go to FIQ, and the remaining channels raise IRQs. This patch adds an optional host map argument to cp_intc_init() for this. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
58 lines
2.3 KiB
C
58 lines
2.3 KiB
C
/*
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* TI Common Platform Interrupt Controller (cp_intc) definitions
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*
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* Author: Steve Chen <schen@mvista.com>
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* Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#ifndef __ASM_HARDWARE_CP_INTC_H
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#define __ASM_HARDWARE_CP_INTC_H
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#define CP_INTC_REV 0x00
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#define CP_INTC_CTRL 0x04
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#define CP_INTC_HOST_CTRL 0x0C
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#define CP_INTC_GLOBAL_ENABLE 0x10
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#define CP_INTC_GLOBAL_NESTING_LEVEL 0x1C
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#define CP_INTC_SYS_STAT_IDX_SET 0x20
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#define CP_INTC_SYS_STAT_IDX_CLR 0x24
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#define CP_INTC_SYS_ENABLE_IDX_SET 0x28
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#define CP_INTC_SYS_ENABLE_IDX_CLR 0x2C
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#define CP_INTC_GLOBAL_WAKEUP_ENABLE 0x30
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#define CP_INTC_HOST_ENABLE_IDX_SET 0x34
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#define CP_INTC_HOST_ENABLE_IDX_CLR 0x38
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#define CP_INTC_PACING_PRESCALE 0x40
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#define CP_INTC_VECTOR_BASE 0x50
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#define CP_INTC_VECTOR_SIZE 0x54
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#define CP_INTC_VECTOR_NULL 0x58
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#define CP_INTC_PRIO_IDX 0x80
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#define CP_INTC_PRIO_VECTOR 0x84
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#define CP_INTC_SECURE_ENABLE 0x90
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#define CP_INTC_SECURE_PRIO_IDX 0x94
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#define CP_INTC_PACING_PARAM(n) (0x0100 + (n << 4))
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#define CP_INTC_PACING_DEC(n) (0x0104 + (n << 4))
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#define CP_INTC_PACING_MAP(n) (0x0108 + (n << 4))
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#define CP_INTC_SYS_RAW_STAT(n) (0x0200 + (n << 2))
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#define CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2))
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#define CP_INTC_SYS_ENABLE_SET(n) (0x0300 + (n << 2))
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#define CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2))
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#define CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2))
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#define CP_INTC_HOST_MAP(n) (0x0800 + (n << 2))
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#define CP_INTC_HOST_PRIO_IDX(n) (0x0900 + (n << 2))
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#define CP_INTC_SYS_POLARITY(n) (0x0D00 + (n << 2))
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#define CP_INTC_SYS_TYPE(n) (0x0D80 + (n << 2))
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#define CP_INTC_WAKEUP_ENABLE(n) (0x0E00 + (n << 2))
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#define CP_INTC_DEBUG_SELECT(n) (0x0F00 + (n << 2))
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#define CP_INTC_SYS_SECURE_ENABLE(n) (0x1000 + (n << 2))
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#define CP_INTC_HOST_NESTING_LEVEL(n) (0x1100 + (n << 2))
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#define CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2))
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#define CP_INTC_HOST_PRIO_VECTOR(n) (0x1600 + (n << 2))
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#define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2))
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void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
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u8 *irq_prio, u32 *host_map);
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#endif /* __ASM_HARDWARE_CP_INTC_H */
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