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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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44893591ea
Add spi controller nodes to the mt7623.dtsi file Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
347 lines
9.0 KiB
Plaintext
347 lines
9.0 KiB
Plaintext
/*
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* Copyright (c) 2016 MediaTek Inc.
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* Author: John Crispin <john@phrozen.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt2701-clk.h>
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#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
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#include <dt-bindings/power/mt2701-power.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/mt2701-resets.h>
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#include "skeleton64.dtsi"
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/ {
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compatible = "mediatek,mt7623";
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interrupt-parent = <&sysirq>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "mediatek,mt6589-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x3>;
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};
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};
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system_clk: dummy13m {
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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#clock-cells = <0>;
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};
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rtc32k: oscillator@1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32000>;
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clock-output-names = "rtc32k";
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};
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clk26m: oscillator@0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "clk26m";
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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topckgen: syscon@10000000 {
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compatible = "mediatek,mt7623-topckgen",
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"mediatek,mt2701-topckgen",
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"syscon";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: syscon@10001000 {
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compatible = "mediatek,mt7623-infracfg",
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"mediatek,mt2701-infracfg",
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"syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pericfg: syscon@10003000 {
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compatible = "mediatek,mt7623-pericfg",
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"mediatek,mt2701-pericfg",
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"syscon";
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reg = <0 0x10003000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt7623-pinctrl",
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"mediatek,mt2701-pinctrl";
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reg = <0 0x1000b000 0 0x1000>;
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mediatek,pctl-regmap = <&syscfg_pctl_a>;
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pins-are-numbered;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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};
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syscfg_pctl_a: syscfg@10005000 {
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compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
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reg = <0 0x10005000 0 0x1000>;
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};
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scpsys: scpsys@10006000 {
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compatible = "mediatek,mt7623-scpsys",
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"mediatek,mt2701-scpsys",
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"syscon";
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#power-domain-cells = <1>;
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reg = <0 0x10006000 0 0x1000>;
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infracfg = <&infracfg>;
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clocks = <&topckgen CLK_TOP_MM_SEL>,
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<&topckgen CLK_TOP_MFG_SEL>,
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<&topckgen CLK_TOP_ETHIF_SEL>;
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clock-names = "mm", "mfg", "ethif";
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};
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watchdog: watchdog@10007000 {
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compatible = "mediatek,mt7623-wdt",
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"mediatek,mt6589-wdt";
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reg = <0 0x10007000 0 0x100>;
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};
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timer: timer@10008000 {
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compatible = "mediatek,mt7623-timer",
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"mediatek,mt6577-timer";
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reg = <0 0x10008000 0 0x80>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&system_clk>, <&rtc32k>;
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clock-names = "system-clk", "rtc-clk";
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};
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pwrap: pwrap@1000d000 {
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compatible = "mediatek,mt7623-pwrap",
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"mediatek,mt2701-pwrap";
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reg = <0 0x1000d000 0 0x1000>;
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reg-names = "pwrap";
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
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reset-names = "pwrap";
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clocks = <&infracfg CLK_INFRA_PMICSPI>,
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<&infracfg CLK_INFRA_PMICWRAP>;
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clock-names = "spi", "wrap";
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};
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sysirq: interrupt-controller@10200100 {
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compatible = "mediatek,mt7623-sysirq",
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"mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10200100 0 0x1c>;
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};
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apmixedsys: syscon@10209000 {
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compatible = "mediatek,mt7623-apmixedsys",
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"mediatek,mt2701-apmixedsys",
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"syscon";
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reg = <0 0x10209000 0 0x1000>;
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#clock-cells = <1>;
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};
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gic: interrupt-controller@10211000 {
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compatible = "arm,cortex-a7-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10211000 0 0x1000>,
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<0 0x10212000 0 0x2000>,
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<0 0x10214000 0 0x2000>,
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<0 0x10216000 0 0x2000>;
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt7623-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x400>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART0_SEL>,
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<&pericfg CLK_PERI_UART0>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt7623-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x400>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART1_SEL>,
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<&pericfg CLK_PERI_UART1>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt7623-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x400>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART2_SEL>,
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<&pericfg CLK_PERI_UART2>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart3: serial@11005000 {
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compatible = "mediatek,mt7623-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11005000 0 0x400>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART3_SEL>,
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<&pericfg CLK_PERI_UART3>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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i2c0: i2c@11007000 {
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compatible = "mediatek,mt7623-i2c",
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"mediatek,mt6577-i2c";
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reg = <0 0x11007000 0 0x70>,
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<0 0x11000200 0 0x80>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C0>,
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<&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@11008000 {
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compatible = "mediatek,mt7623-i2c",
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"mediatek,mt6577-i2c";
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reg = <0 0x11008000 0 0x70>,
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<0 0x11000280 0 0x80>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C1>,
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<&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@11009000 {
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compatible = "mediatek,mt7623-i2c",
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"mediatek,mt6577-i2c";
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reg = <0 0x11009000 0 0x70>,
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<0 0x11000300 0 0x80>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C2>,
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<&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi0: spi@1100a000 {
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compatible = "mediatek,mt7623-spi",
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"mediatek,mt2701-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x1100a000 0 0x100>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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<&topckgen CLK_TOP_SPI0_SEL>,
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<&pericfg CLK_PERI_SPI0>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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status = "disabled";
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};
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spi1: spi@11016000 {
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compatible = "mediatek,mt7623-spi",
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"mediatek,mt2701-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x11016000 0 0x100>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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<&topckgen CLK_TOP_SPI1_SEL>,
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<&pericfg CLK_PERI_SPI1>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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status = "disabled";
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};
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spi2: spi@11017000 {
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compatible = "mediatek,mt7623-spi",
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"mediatek,mt2701-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x11017000 0 0x1000>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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<&topckgen CLK_TOP_SPI2_SEL>,
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<&pericfg CLK_PERI_SPI2>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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status = "disabled";
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};
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hifsys: syscon@1a000000 {
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compatible = "mediatek,mt7623-hifsys",
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"mediatek,mt2701-hifsys",
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"syscon";
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reg = <0 0x1a000000 0 0x1000>;
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#clock-cells = <1>;
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};
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ethsys: syscon@1b000000 {
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compatible = "mediatek,mt7623-ethsys",
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"mediatek,mt2701-ethsys",
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"syscon";
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reg = <0 0x1b000000 0 0x1000>;
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#clock-cells = <1>;
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};
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};
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