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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ee2f573c42
Pins used as GPIO interrupts need to be configured as EINTs. This patch adds the required configuration code to exynos_gpio_irq_set_type, to set the pin as EINT when its interrupt trigger is configured. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
219 lines
8.4 KiB
C
219 lines
8.4 KiB
C
/*
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* Exynos specific definitions for Samsung pinctrl and gpiolib driver.
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Copyright (c) 2012 Linaro Ltd
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* http://www.linaro.org
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*
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* This file contains the Exynos specific definitions for the Samsung
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* pinctrl/gpiolib interface drivers.
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*
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* Author: Thomas Abraham <thomas.ab@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#define EXYNOS_GPIO_START(__gpio) ((__gpio##_START) + (__gpio##_NR))
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#define EXYNOS4210_GPIO_A0_NR (8)
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#define EXYNOS4210_GPIO_A1_NR (6)
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#define EXYNOS4210_GPIO_B_NR (8)
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#define EXYNOS4210_GPIO_C0_NR (5)
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#define EXYNOS4210_GPIO_C1_NR (5)
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#define EXYNOS4210_GPIO_D0_NR (4)
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#define EXYNOS4210_GPIO_D1_NR (4)
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#define EXYNOS4210_GPIO_E0_NR (5)
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#define EXYNOS4210_GPIO_E1_NR (8)
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#define EXYNOS4210_GPIO_E2_NR (6)
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#define EXYNOS4210_GPIO_E3_NR (8)
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#define EXYNOS4210_GPIO_E4_NR (8)
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#define EXYNOS4210_GPIO_F0_NR (8)
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#define EXYNOS4210_GPIO_F1_NR (8)
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#define EXYNOS4210_GPIO_F2_NR (8)
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#define EXYNOS4210_GPIO_F3_NR (6)
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#define EXYNOS4210_GPIO_J0_NR (8)
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#define EXYNOS4210_GPIO_J1_NR (5)
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#define EXYNOS4210_GPIO_K0_NR (7)
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#define EXYNOS4210_GPIO_K1_NR (7)
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#define EXYNOS4210_GPIO_K2_NR (7)
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#define EXYNOS4210_GPIO_K3_NR (7)
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#define EXYNOS4210_GPIO_L0_NR (8)
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#define EXYNOS4210_GPIO_L1_NR (3)
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#define EXYNOS4210_GPIO_L2_NR (8)
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#define EXYNOS4210_GPIO_Y0_NR (6)
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#define EXYNOS4210_GPIO_Y1_NR (4)
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#define EXYNOS4210_GPIO_Y2_NR (6)
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#define EXYNOS4210_GPIO_Y3_NR (8)
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#define EXYNOS4210_GPIO_Y4_NR (8)
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#define EXYNOS4210_GPIO_Y5_NR (8)
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#define EXYNOS4210_GPIO_Y6_NR (8)
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#define EXYNOS4210_GPIO_X0_NR (8)
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#define EXYNOS4210_GPIO_X1_NR (8)
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#define EXYNOS4210_GPIO_X2_NR (8)
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#define EXYNOS4210_GPIO_X3_NR (8)
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#define EXYNOS4210_GPIO_Z_NR (7)
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enum exynos4210_gpio_xa_start {
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EXYNOS4210_GPIO_A0_START = 0,
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EXYNOS4210_GPIO_A1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_A0),
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EXYNOS4210_GPIO_B_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_A1),
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EXYNOS4210_GPIO_C0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_B),
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EXYNOS4210_GPIO_C1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_C0),
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EXYNOS4210_GPIO_D0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_C1),
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EXYNOS4210_GPIO_D1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_D0),
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EXYNOS4210_GPIO_E0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_D1),
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EXYNOS4210_GPIO_E1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E0),
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EXYNOS4210_GPIO_E2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E1),
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EXYNOS4210_GPIO_E3_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E2),
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EXYNOS4210_GPIO_E4_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E3),
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EXYNOS4210_GPIO_F0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E4),
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EXYNOS4210_GPIO_F1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_F0),
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EXYNOS4210_GPIO_F2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_F1),
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EXYNOS4210_GPIO_F3_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_F2),
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};
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enum exynos4210_gpio_xb_start {
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EXYNOS4210_GPIO_J0_START = 0,
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EXYNOS4210_GPIO_J1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_J0),
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EXYNOS4210_GPIO_K0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_J1),
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EXYNOS4210_GPIO_K1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_K0),
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EXYNOS4210_GPIO_K2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_K1),
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EXYNOS4210_GPIO_K3_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_K2),
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EXYNOS4210_GPIO_L0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_K3),
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EXYNOS4210_GPIO_L1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_L0),
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EXYNOS4210_GPIO_L2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_L1),
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EXYNOS4210_GPIO_Y0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_L2),
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EXYNOS4210_GPIO_Y1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y0),
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EXYNOS4210_GPIO_Y2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y1),
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EXYNOS4210_GPIO_Y3_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y2),
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EXYNOS4210_GPIO_Y4_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y3),
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EXYNOS4210_GPIO_Y5_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y4),
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EXYNOS4210_GPIO_Y6_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y5),
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EXYNOS4210_GPIO_X0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y6),
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EXYNOS4210_GPIO_X1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_X0),
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EXYNOS4210_GPIO_X2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_X1),
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EXYNOS4210_GPIO_X3_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_X2),
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};
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enum exynos4210_gpio_xc_start {
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EXYNOS4210_GPIO_Z_START = 0,
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};
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#define EXYNOS4210_GPIO_A0_IRQ EXYNOS4210_GPIO_A0_START
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#define EXYNOS4210_GPIO_A1_IRQ EXYNOS4210_GPIO_A1_START
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#define EXYNOS4210_GPIO_B_IRQ EXYNOS4210_GPIO_B_START
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#define EXYNOS4210_GPIO_C0_IRQ EXYNOS4210_GPIO_C0_START
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#define EXYNOS4210_GPIO_C1_IRQ EXYNOS4210_GPIO_C1_START
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#define EXYNOS4210_GPIO_D0_IRQ EXYNOS4210_GPIO_D0_START
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#define EXYNOS4210_GPIO_D1_IRQ EXYNOS4210_GPIO_D1_START
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#define EXYNOS4210_GPIO_E0_IRQ EXYNOS4210_GPIO_E0_START
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#define EXYNOS4210_GPIO_E1_IRQ EXYNOS4210_GPIO_E1_START
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#define EXYNOS4210_GPIO_E2_IRQ EXYNOS4210_GPIO_E2_START
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#define EXYNOS4210_GPIO_E3_IRQ EXYNOS4210_GPIO_E3_START
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#define EXYNOS4210_GPIO_E4_IRQ EXYNOS4210_GPIO_E4_START
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#define EXYNOS4210_GPIO_F0_IRQ EXYNOS4210_GPIO_F0_START
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#define EXYNOS4210_GPIO_F1_IRQ EXYNOS4210_GPIO_F1_START
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#define EXYNOS4210_GPIO_F2_IRQ EXYNOS4210_GPIO_F2_START
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#define EXYNOS4210_GPIO_F3_IRQ EXYNOS4210_GPIO_F3_START
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#define EXYNOS4210_GPIO_J0_IRQ EXYNOS4210_GPIO_J0_START
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#define EXYNOS4210_GPIO_J1_IRQ EXYNOS4210_GPIO_J1_START
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#define EXYNOS4210_GPIO_K0_IRQ EXYNOS4210_GPIO_K0_START
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#define EXYNOS4210_GPIO_K1_IRQ EXYNOS4210_GPIO_K1_START
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#define EXYNOS4210_GPIO_K2_IRQ EXYNOS4210_GPIO_K2_START
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#define EXYNOS4210_GPIO_K3_IRQ EXYNOS4210_GPIO_K3_START
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#define EXYNOS4210_GPIO_L0_IRQ EXYNOS4210_GPIO_L0_START
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#define EXYNOS4210_GPIO_L1_IRQ EXYNOS4210_GPIO_L1_START
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#define EXYNOS4210_GPIO_L2_IRQ EXYNOS4210_GPIO_L2_START
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#define EXYNOS4210_GPIO_Z_IRQ EXYNOS4210_GPIO_Z_START
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#define EXYNOS4210_GPIOA_NR_PINS EXYNOS_GPIO_START(EXYNOS4210_GPIO_F3)
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#define EXYNOS4210_GPIOA_NR_GINT EXYNOS_GPIO_START(EXYNOS4210_GPIO_F3)
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#define EXYNOS4210_GPIOB_NR_PINS EXYNOS_GPIO_START(EXYNOS4210_GPIO_X3)
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#define EXYNOS4210_GPIOB_NR_GINT EXYNOS_GPIO_START(EXYNOS4210_GPIO_L2)
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#define EXYNOS4210_GPIOC_NR_PINS EXYNOS_GPIO_START(EXYNOS4210_GPIO_Z)
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/* External GPIO and wakeup interrupt related definitions */
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#define EXYNOS_GPIO_ECON_OFFSET 0x700
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#define EXYNOS_GPIO_EMASK_OFFSET 0x900
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#define EXYNOS_GPIO_EPEND_OFFSET 0xA00
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#define EXYNOS_WKUP_ECON_OFFSET 0xE00
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#define EXYNOS_WKUP_EMASK_OFFSET 0xF00
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#define EXYNOS_WKUP_EPEND_OFFSET 0xF40
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#define EXYNOS_SVC_OFFSET 0xB08
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#define EXYNOS_EINT_FUNC 0xF
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/* helpers to access interrupt service register */
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#define EXYNOS_SVC_GROUP_SHIFT 3
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#define EXYNOS_SVC_GROUP_MASK 0x1f
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#define EXYNOS_SVC_NUM_MASK 7
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#define EXYNOS_SVC_GROUP(x) ((x >> EXYNOS_SVC_GROUP_SHIFT) & \
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EXYNOS_SVC_GROUP_MASK)
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/* Exynos specific external interrupt trigger types */
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#define EXYNOS_EINT_LEVEL_LOW 0
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#define EXYNOS_EINT_LEVEL_HIGH 1
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#define EXYNOS_EINT_EDGE_FALLING 2
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#define EXYNOS_EINT_EDGE_RISING 3
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#define EXYNOS_EINT_EDGE_BOTH 4
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#define EXYNOS_EINT_CON_MASK 0xF
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#define EXYNOS_EINT_CON_LEN 4
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#define EXYNOS_EINT_MAX_PER_BANK 8
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#define EXYNOS_EINT_NR_WKUP_EINT
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#define EXYNOS_PIN_BANK_EINTN(reg, __gpio, id) \
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{ \
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.pctl_offset = reg, \
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.pin_base = (__gpio##_START), \
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.nr_pins = (__gpio##_NR), \
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.func_width = 4, \
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.pud_width = 2, \
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.drv_width = 2, \
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.conpdn_width = 2, \
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.pudpdn_width = 2, \
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.eint_type = EINT_TYPE_NONE, \
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.name = id \
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}
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#define EXYNOS_PIN_BANK_EINTG(reg, __gpio, id) \
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{ \
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.pctl_offset = reg, \
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.pin_base = (__gpio##_START), \
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.nr_pins = (__gpio##_NR), \
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.func_width = 4, \
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.pud_width = 2, \
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.drv_width = 2, \
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.conpdn_width = 2, \
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.pudpdn_width = 2, \
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.eint_type = EINT_TYPE_GPIO, \
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.irq_base = (__gpio##_IRQ), \
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.name = id \
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}
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/**
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* struct exynos_geint_data: gpio eint specific data for irq_chip callbacks.
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* @bank: pin bank from which this gpio interrupt originates.
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* @pin: pin number within the bank.
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* @eint_offset: offset to be added to the con/pend/mask register bank base.
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*/
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struct exynos_geint_data {
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struct samsung_pin_bank *bank;
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u32 pin;
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u32 eint_offset;
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};
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/**
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* struct exynos_weint_data: irq specific data for all the wakeup interrupts
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* generated by the external wakeup interrupt controller.
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* @domain: irq domain representing the external wakeup interrupts
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* @irq: interrupt number within the domain.
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*/
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struct exynos_weint_data {
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struct irq_domain *domain;
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u32 irq;
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};
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