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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 19:36:39 +07:00
6896bcd198
Even if both drivers are compiled in only one instance can run on a given system depending on the available GIC version. So having seperate hotplug states for them is pointless. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Sebastian Siewior <bigeasy@linutronix.de> Link: http://lkml.kernel.org/r/20161221192112.252416267@linutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
1483 lines
35 KiB
C
1483 lines
35 KiB
C
/*
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* Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define pr_fmt(fmt) "GICv3: " fmt
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#include <linux/acpi.h>
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#include <linux/cpu.h>
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#include <linux/cpu_pm.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/percpu.h>
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#include <linux/slab.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/arm-gic-common.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <linux/irqchip/irq-partition-percpu.h>
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#include <asm/cputype.h>
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#include <asm/exception.h>
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#include <asm/smp_plat.h>
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#include <asm/virt.h>
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#include "irq-gic-common.h"
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struct redist_region {
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void __iomem *redist_base;
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phys_addr_t phys_base;
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bool single_redist;
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};
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struct gic_chip_data {
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struct fwnode_handle *fwnode;
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void __iomem *dist_base;
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struct redist_region *redist_regions;
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struct rdists rdists;
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struct irq_domain *domain;
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u64 redist_stride;
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u32 nr_redist_regions;
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unsigned int irq_nr;
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struct partition_desc *ppi_descs[16];
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};
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static struct gic_chip_data gic_data __read_mostly;
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static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
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static struct gic_kvm_info gic_v3_kvm_info;
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#define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist))
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#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
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#define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
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/* Our default, arbitrary priority value. Linux only uses one anyway. */
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#define DEFAULT_PMR_VALUE 0xf0
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static inline unsigned int gic_irq(struct irq_data *d)
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{
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return d->hwirq;
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}
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static inline int gic_irq_in_rdist(struct irq_data *d)
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{
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return gic_irq(d) < 32;
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}
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static inline void __iomem *gic_dist_base(struct irq_data *d)
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{
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if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */
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return gic_data_rdist_sgi_base();
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if (d->hwirq <= 1023) /* SPI -> dist_base */
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return gic_data.dist_base;
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return NULL;
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}
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static void gic_do_wait_for_rwp(void __iomem *base)
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{
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u32 count = 1000000; /* 1s! */
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while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
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count--;
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if (!count) {
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pr_err_ratelimited("RWP timeout, gone fishing\n");
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return;
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}
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cpu_relax();
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udelay(1);
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};
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}
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/* Wait for completion of a distributor change */
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static void gic_dist_wait_for_rwp(void)
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{
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gic_do_wait_for_rwp(gic_data.dist_base);
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}
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/* Wait for completion of a redistributor change */
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static void gic_redist_wait_for_rwp(void)
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{
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gic_do_wait_for_rwp(gic_data_rdist_rd_base());
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}
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#ifdef CONFIG_ARM64
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static u64 __maybe_unused gic_read_iar(void)
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{
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if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154))
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return gic_read_iar_cavium_thunderx();
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else
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return gic_read_iar_common();
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}
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#endif
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static void gic_enable_redist(bool enable)
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{
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void __iomem *rbase;
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u32 count = 1000000; /* 1s! */
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u32 val;
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rbase = gic_data_rdist_rd_base();
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val = readl_relaxed(rbase + GICR_WAKER);
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if (enable)
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/* Wake up this CPU redistributor */
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val &= ~GICR_WAKER_ProcessorSleep;
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else
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val |= GICR_WAKER_ProcessorSleep;
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writel_relaxed(val, rbase + GICR_WAKER);
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if (!enable) { /* Check that GICR_WAKER is writeable */
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val = readl_relaxed(rbase + GICR_WAKER);
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if (!(val & GICR_WAKER_ProcessorSleep))
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return; /* No PM support in this redistributor */
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}
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while (--count) {
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val = readl_relaxed(rbase + GICR_WAKER);
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if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep))
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break;
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cpu_relax();
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udelay(1);
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};
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if (!count)
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pr_err_ratelimited("redistributor failed to %s...\n",
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enable ? "wakeup" : "sleep");
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}
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/*
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* Routines to disable, enable, EOI and route interrupts
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*/
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static int gic_peek_irq(struct irq_data *d, u32 offset)
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{
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u32 mask = 1 << (gic_irq(d) % 32);
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void __iomem *base;
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if (gic_irq_in_rdist(d))
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base = gic_data_rdist_sgi_base();
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else
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base = gic_data.dist_base;
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return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
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}
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static void gic_poke_irq(struct irq_data *d, u32 offset)
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{
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u32 mask = 1 << (gic_irq(d) % 32);
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void (*rwp_wait)(void);
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void __iomem *base;
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if (gic_irq_in_rdist(d)) {
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base = gic_data_rdist_sgi_base();
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rwp_wait = gic_redist_wait_for_rwp;
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} else {
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base = gic_data.dist_base;
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rwp_wait = gic_dist_wait_for_rwp;
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}
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writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4);
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rwp_wait();
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}
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static void gic_mask_irq(struct irq_data *d)
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{
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gic_poke_irq(d, GICD_ICENABLER);
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}
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static void gic_eoimode1_mask_irq(struct irq_data *d)
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{
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gic_mask_irq(d);
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/*
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* When masking a forwarded interrupt, make sure it is
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* deactivated as well.
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*
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* This ensures that an interrupt that is getting
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* disabled/masked will not get "stuck", because there is
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* noone to deactivate it (guest is being terminated).
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*/
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if (irqd_is_forwarded_to_vcpu(d))
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gic_poke_irq(d, GICD_ICACTIVER);
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}
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static void gic_unmask_irq(struct irq_data *d)
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{
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gic_poke_irq(d, GICD_ISENABLER);
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}
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static int gic_irq_set_irqchip_state(struct irq_data *d,
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enum irqchip_irq_state which, bool val)
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{
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u32 reg;
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if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
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return -EINVAL;
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switch (which) {
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case IRQCHIP_STATE_PENDING:
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reg = val ? GICD_ISPENDR : GICD_ICPENDR;
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break;
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case IRQCHIP_STATE_ACTIVE:
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reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
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break;
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case IRQCHIP_STATE_MASKED:
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reg = val ? GICD_ICENABLER : GICD_ISENABLER;
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break;
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default:
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return -EINVAL;
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}
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gic_poke_irq(d, reg);
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return 0;
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}
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static int gic_irq_get_irqchip_state(struct irq_data *d,
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enum irqchip_irq_state which, bool *val)
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{
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if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
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return -EINVAL;
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switch (which) {
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case IRQCHIP_STATE_PENDING:
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*val = gic_peek_irq(d, GICD_ISPENDR);
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break;
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case IRQCHIP_STATE_ACTIVE:
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*val = gic_peek_irq(d, GICD_ISACTIVER);
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break;
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case IRQCHIP_STATE_MASKED:
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*val = !gic_peek_irq(d, GICD_ISENABLER);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static void gic_eoi_irq(struct irq_data *d)
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{
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gic_write_eoir(gic_irq(d));
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}
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static void gic_eoimode1_eoi_irq(struct irq_data *d)
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{
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/*
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* No need to deactivate an LPI, or an interrupt that
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* is is getting forwarded to a vcpu.
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*/
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if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
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return;
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gic_write_dir(gic_irq(d));
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}
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static int gic_set_type(struct irq_data *d, unsigned int type)
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{
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unsigned int irq = gic_irq(d);
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void (*rwp_wait)(void);
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void __iomem *base;
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/* Interrupt configuration for SGIs can't be changed */
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if (irq < 16)
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return -EINVAL;
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/* SPIs have restrictions on the supported types */
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if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
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type != IRQ_TYPE_EDGE_RISING)
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return -EINVAL;
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if (gic_irq_in_rdist(d)) {
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base = gic_data_rdist_sgi_base();
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rwp_wait = gic_redist_wait_for_rwp;
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} else {
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base = gic_data.dist_base;
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rwp_wait = gic_dist_wait_for_rwp;
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}
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return gic_configure_irq(irq, type, base, rwp_wait);
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}
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static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
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{
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if (vcpu)
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irqd_set_forwarded_to_vcpu(d);
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else
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irqd_clr_forwarded_to_vcpu(d);
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return 0;
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}
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static u64 gic_mpidr_to_affinity(unsigned long mpidr)
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{
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u64 aff;
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aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
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MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
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MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
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MPIDR_AFFINITY_LEVEL(mpidr, 0));
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return aff;
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}
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static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
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{
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u32 irqnr;
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do {
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irqnr = gic_read_iar();
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if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) {
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int err;
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if (static_key_true(&supports_deactivate))
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gic_write_eoir(irqnr);
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err = handle_domain_irq(gic_data.domain, irqnr, regs);
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if (err) {
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WARN_ONCE(true, "Unexpected interrupt received!\n");
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if (static_key_true(&supports_deactivate)) {
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if (irqnr < 8192)
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gic_write_dir(irqnr);
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} else {
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gic_write_eoir(irqnr);
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}
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}
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continue;
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}
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if (irqnr < 16) {
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gic_write_eoir(irqnr);
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if (static_key_true(&supports_deactivate))
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gic_write_dir(irqnr);
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#ifdef CONFIG_SMP
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/*
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* Unlike GICv2, we don't need an smp_rmb() here.
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* The control dependency from gic_read_iar to
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* the ISB in gic_write_eoir is enough to ensure
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* that any shared data read by handle_IPI will
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* be read after the ACK.
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*/
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handle_IPI(irqnr, regs);
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#else
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WARN_ONCE(true, "Unexpected SGI received!\n");
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#endif
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continue;
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}
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} while (irqnr != ICC_IAR1_EL1_SPURIOUS);
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}
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static void __init gic_dist_init(void)
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{
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unsigned int i;
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u64 affinity;
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void __iomem *base = gic_data.dist_base;
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/* Disable the distributor */
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writel_relaxed(0, base + GICD_CTLR);
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gic_dist_wait_for_rwp();
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/*
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* Configure SPIs as non-secure Group-1. This will only matter
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* if the GIC only has a single security state. This will not
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* do the right thing if the kernel is running in secure mode,
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* but that's not the intended use case anyway.
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*/
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for (i = 32; i < gic_data.irq_nr; i += 32)
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writel_relaxed(~0, base + GICD_IGROUPR + i / 8);
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gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);
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/* Enable distributor with ARE, Group1 */
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writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
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base + GICD_CTLR);
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/*
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* Set all global interrupts to the boot CPU only. ARE must be
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* enabled.
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*/
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affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
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for (i = 32; i < gic_data.irq_nr; i++)
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gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
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}
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static int gic_populate_rdist(void)
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{
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unsigned long mpidr = cpu_logical_map(smp_processor_id());
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u64 typer;
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u32 aff;
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int i;
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/*
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* Convert affinity to a 32bit value that can be matched to
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* GICR_TYPER bits [63:32].
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*/
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aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
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MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
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MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
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MPIDR_AFFINITY_LEVEL(mpidr, 0));
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for (i = 0; i < gic_data.nr_redist_regions; i++) {
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void __iomem *ptr = gic_data.redist_regions[i].redist_base;
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u32 reg;
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reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
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if (reg != GIC_PIDR2_ARCH_GICv3 &&
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reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
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pr_warn("No redistributor present @%p\n", ptr);
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break;
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}
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do {
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typer = gic_read_typer(ptr + GICR_TYPER);
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if ((typer >> 32) == aff) {
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u64 offset = ptr - gic_data.redist_regions[i].redist_base;
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gic_data_rdist_rd_base() = ptr;
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gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset;
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pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
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smp_processor_id(), mpidr, i,
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&gic_data_rdist()->phys_base);
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return 0;
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}
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if (gic_data.redist_regions[i].single_redist)
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break;
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if (gic_data.redist_stride) {
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ptr += gic_data.redist_stride;
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} else {
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ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
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if (typer & GICR_TYPER_VLPIS)
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ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
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}
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} while (!(typer & GICR_TYPER_LAST));
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}
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/* We couldn't even deal with ourselves... */
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WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
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smp_processor_id(), mpidr);
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return -ENODEV;
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}
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static void gic_cpu_sys_reg_init(void)
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{
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/*
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* Need to check that the SRE bit has actually been set. If
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* not, it means that SRE is disabled at EL2. We're going to
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|
* die painfully, and there is nothing we can do about it.
|
|
*
|
|
* Kindly inform the luser.
|
|
*/
|
|
if (!gic_enable_sre())
|
|
pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
|
|
|
|
/* Set priority mask register */
|
|
gic_write_pmr(DEFAULT_PMR_VALUE);
|
|
|
|
/*
|
|
* Some firmwares hand over to the kernel with the BPR changed from
|
|
* its reset value (and with a value large enough to prevent
|
|
* any pre-emptive interrupts from working at all). Writing a zero
|
|
* to BPR restores is reset value.
|
|
*/
|
|
gic_write_bpr1(0);
|
|
|
|
if (static_key_true(&supports_deactivate)) {
|
|
/* EOI drops priority only (mode 1) */
|
|
gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
|
|
} else {
|
|
/* EOI deactivates interrupt too (mode 0) */
|
|
gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
|
|
}
|
|
|
|
/* ... and let's hit the road... */
|
|
gic_write_grpen1(1);
|
|
}
|
|
|
|
static int gic_dist_supports_lpis(void)
|
|
{
|
|
return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS);
|
|
}
|
|
|
|
static void gic_cpu_init(void)
|
|
{
|
|
void __iomem *rbase;
|
|
|
|
/* Register ourselves with the rest of the world */
|
|
if (gic_populate_rdist())
|
|
return;
|
|
|
|
gic_enable_redist(true);
|
|
|
|
rbase = gic_data_rdist_sgi_base();
|
|
|
|
/* Configure SGIs/PPIs as non-secure Group-1 */
|
|
writel_relaxed(~0, rbase + GICR_IGROUPR0);
|
|
|
|
gic_cpu_config(rbase, gic_redist_wait_for_rwp);
|
|
|
|
/* Give LPIs a spin */
|
|
if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
|
|
its_cpu_init();
|
|
|
|
/* initialise system registers */
|
|
gic_cpu_sys_reg_init();
|
|
}
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
static int gic_starting_cpu(unsigned int cpu)
|
|
{
|
|
gic_cpu_init();
|
|
return 0;
|
|
}
|
|
|
|
static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
|
|
unsigned long cluster_id)
|
|
{
|
|
int next_cpu, cpu = *base_cpu;
|
|
unsigned long mpidr = cpu_logical_map(cpu);
|
|
u16 tlist = 0;
|
|
|
|
while (cpu < nr_cpu_ids) {
|
|
/*
|
|
* If we ever get a cluster of more than 16 CPUs, just
|
|
* scream and skip that CPU.
|
|
*/
|
|
if (WARN_ON((mpidr & 0xff) >= 16))
|
|
goto out;
|
|
|
|
tlist |= 1 << (mpidr & 0xf);
|
|
|
|
next_cpu = cpumask_next(cpu, mask);
|
|
if (next_cpu >= nr_cpu_ids)
|
|
goto out;
|
|
cpu = next_cpu;
|
|
|
|
mpidr = cpu_logical_map(cpu);
|
|
|
|
if (cluster_id != (mpidr & ~0xffUL)) {
|
|
cpu--;
|
|
goto out;
|
|
}
|
|
}
|
|
out:
|
|
*base_cpu = cpu;
|
|
return tlist;
|
|
}
|
|
|
|
#define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
|
|
(MPIDR_AFFINITY_LEVEL(cluster_id, level) \
|
|
<< ICC_SGI1R_AFFINITY_## level ##_SHIFT)
|
|
|
|
static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
|
|
{
|
|
u64 val;
|
|
|
|
val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) |
|
|
MPIDR_TO_SGI_AFFINITY(cluster_id, 2) |
|
|
irq << ICC_SGI1R_SGI_ID_SHIFT |
|
|
MPIDR_TO_SGI_AFFINITY(cluster_id, 1) |
|
|
tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
|
|
|
|
pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
|
|
gic_write_sgi1r(val);
|
|
}
|
|
|
|
static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
|
|
{
|
|
int cpu;
|
|
|
|
if (WARN_ON(irq >= 16))
|
|
return;
|
|
|
|
/*
|
|
* Ensure that stores to Normal memory are visible to the
|
|
* other CPUs before issuing the IPI.
|
|
*/
|
|
smp_wmb();
|
|
|
|
for_each_cpu(cpu, mask) {
|
|
unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL;
|
|
u16 tlist;
|
|
|
|
tlist = gic_compute_target_list(&cpu, mask, cluster_id);
|
|
gic_send_sgi(cluster_id, tlist, irq);
|
|
}
|
|
|
|
/* Force the above writes to ICC_SGI1R_EL1 to be executed */
|
|
isb();
|
|
}
|
|
|
|
static void gic_smp_init(void)
|
|
{
|
|
set_smp_cross_call(gic_raise_softirq);
|
|
cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
|
|
"irqchip/arm/gicv3:starting",
|
|
gic_starting_cpu, NULL);
|
|
}
|
|
|
|
static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
|
|
bool force)
|
|
{
|
|
unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
|
|
void __iomem *reg;
|
|
int enabled;
|
|
u64 val;
|
|
|
|
if (gic_irq_in_rdist(d))
|
|
return -EINVAL;
|
|
|
|
/* If interrupt was enabled, disable it first */
|
|
enabled = gic_peek_irq(d, GICD_ISENABLER);
|
|
if (enabled)
|
|
gic_mask_irq(d);
|
|
|
|
reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
|
|
val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
|
|
|
|
gic_write_irouter(val, reg);
|
|
|
|
/*
|
|
* If the interrupt was enabled, enabled it again. Otherwise,
|
|
* just wait for the distributor to have digested our changes.
|
|
*/
|
|
if (enabled)
|
|
gic_unmask_irq(d);
|
|
else
|
|
gic_dist_wait_for_rwp();
|
|
|
|
return IRQ_SET_MASK_OK_DONE;
|
|
}
|
|
#else
|
|
#define gic_set_affinity NULL
|
|
#define gic_smp_init() do { } while(0)
|
|
#endif
|
|
|
|
#ifdef CONFIG_CPU_PM
|
|
/* Check whether it's single security state view */
|
|
static bool gic_dist_security_disabled(void)
|
|
{
|
|
return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS;
|
|
}
|
|
|
|
static int gic_cpu_pm_notifier(struct notifier_block *self,
|
|
unsigned long cmd, void *v)
|
|
{
|
|
if (cmd == CPU_PM_EXIT) {
|
|
if (gic_dist_security_disabled())
|
|
gic_enable_redist(true);
|
|
gic_cpu_sys_reg_init();
|
|
} else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) {
|
|
gic_write_grpen1(0);
|
|
gic_enable_redist(false);
|
|
}
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static struct notifier_block gic_cpu_pm_notifier_block = {
|
|
.notifier_call = gic_cpu_pm_notifier,
|
|
};
|
|
|
|
static void gic_cpu_pm_init(void)
|
|
{
|
|
cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
|
|
}
|
|
|
|
#else
|
|
static inline void gic_cpu_pm_init(void) { }
|
|
#endif /* CONFIG_CPU_PM */
|
|
|
|
static struct irq_chip gic_chip = {
|
|
.name = "GICv3",
|
|
.irq_mask = gic_mask_irq,
|
|
.irq_unmask = gic_unmask_irq,
|
|
.irq_eoi = gic_eoi_irq,
|
|
.irq_set_type = gic_set_type,
|
|
.irq_set_affinity = gic_set_affinity,
|
|
.irq_get_irqchip_state = gic_irq_get_irqchip_state,
|
|
.irq_set_irqchip_state = gic_irq_set_irqchip_state,
|
|
.flags = IRQCHIP_SET_TYPE_MASKED,
|
|
};
|
|
|
|
static struct irq_chip gic_eoimode1_chip = {
|
|
.name = "GICv3",
|
|
.irq_mask = gic_eoimode1_mask_irq,
|
|
.irq_unmask = gic_unmask_irq,
|
|
.irq_eoi = gic_eoimode1_eoi_irq,
|
|
.irq_set_type = gic_set_type,
|
|
.irq_set_affinity = gic_set_affinity,
|
|
.irq_get_irqchip_state = gic_irq_get_irqchip_state,
|
|
.irq_set_irqchip_state = gic_irq_set_irqchip_state,
|
|
.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
|
|
.flags = IRQCHIP_SET_TYPE_MASKED,
|
|
};
|
|
|
|
#define GIC_ID_NR (1U << gic_data.rdists.id_bits)
|
|
|
|
static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
|
|
irq_hw_number_t hw)
|
|
{
|
|
struct irq_chip *chip = &gic_chip;
|
|
|
|
if (static_key_true(&supports_deactivate))
|
|
chip = &gic_eoimode1_chip;
|
|
|
|
/* SGIs are private to the core kernel */
|
|
if (hw < 16)
|
|
return -EPERM;
|
|
/* Nothing here */
|
|
if (hw >= gic_data.irq_nr && hw < 8192)
|
|
return -EPERM;
|
|
/* Off limits */
|
|
if (hw >= GIC_ID_NR)
|
|
return -EPERM;
|
|
|
|
/* PPIs */
|
|
if (hw < 32) {
|
|
irq_set_percpu_devid(irq);
|
|
irq_domain_set_info(d, irq, hw, chip, d->host_data,
|
|
handle_percpu_devid_irq, NULL, NULL);
|
|
irq_set_status_flags(irq, IRQ_NOAUTOEN);
|
|
}
|
|
/* SPIs */
|
|
if (hw >= 32 && hw < gic_data.irq_nr) {
|
|
irq_domain_set_info(d, irq, hw, chip, d->host_data,
|
|
handle_fasteoi_irq, NULL, NULL);
|
|
irq_set_probe(irq);
|
|
}
|
|
/* LPIs */
|
|
if (hw >= 8192 && hw < GIC_ID_NR) {
|
|
if (!gic_dist_supports_lpis())
|
|
return -EPERM;
|
|
irq_domain_set_info(d, irq, hw, chip, d->host_data,
|
|
handle_fasteoi_irq, NULL, NULL);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gic_irq_domain_translate(struct irq_domain *d,
|
|
struct irq_fwspec *fwspec,
|
|
unsigned long *hwirq,
|
|
unsigned int *type)
|
|
{
|
|
if (is_of_node(fwspec->fwnode)) {
|
|
if (fwspec->param_count < 3)
|
|
return -EINVAL;
|
|
|
|
switch (fwspec->param[0]) {
|
|
case 0: /* SPI */
|
|
*hwirq = fwspec->param[1] + 32;
|
|
break;
|
|
case 1: /* PPI */
|
|
*hwirq = fwspec->param[1] + 16;
|
|
break;
|
|
case GIC_IRQ_TYPE_LPI: /* LPI */
|
|
*hwirq = fwspec->param[1];
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
|
|
return 0;
|
|
}
|
|
|
|
if (is_fwnode_irqchip(fwspec->fwnode)) {
|
|
if(fwspec->param_count != 2)
|
|
return -EINVAL;
|
|
|
|
*hwirq = fwspec->param[0];
|
|
*type = fwspec->param[1];
|
|
return 0;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
|
|
unsigned int nr_irqs, void *arg)
|
|
{
|
|
int i, ret;
|
|
irq_hw_number_t hwirq;
|
|
unsigned int type = IRQ_TYPE_NONE;
|
|
struct irq_fwspec *fwspec = arg;
|
|
|
|
ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
|
|
if (ret)
|
|
return ret;
|
|
|
|
for (i = 0; i < nr_irqs; i++)
|
|
gic_irq_domain_map(domain, virq + i, hwirq + i);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
|
|
unsigned int nr_irqs)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < nr_irqs; i++) {
|
|
struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
|
|
irq_set_handler(virq + i, NULL);
|
|
irq_domain_reset_irq_data(d);
|
|
}
|
|
}
|
|
|
|
static int gic_irq_domain_select(struct irq_domain *d,
|
|
struct irq_fwspec *fwspec,
|
|
enum irq_domain_bus_token bus_token)
|
|
{
|
|
/* Not for us */
|
|
if (fwspec->fwnode != d->fwnode)
|
|
return 0;
|
|
|
|
/* If this is not DT, then we have a single domain */
|
|
if (!is_of_node(fwspec->fwnode))
|
|
return 1;
|
|
|
|
/*
|
|
* If this is a PPI and we have a 4th (non-null) parameter,
|
|
* then we need to match the partition domain.
|
|
*/
|
|
if (fwspec->param_count >= 4 &&
|
|
fwspec->param[0] == 1 && fwspec->param[3] != 0)
|
|
return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]);
|
|
|
|
return d == gic_data.domain;
|
|
}
|
|
|
|
static const struct irq_domain_ops gic_irq_domain_ops = {
|
|
.translate = gic_irq_domain_translate,
|
|
.alloc = gic_irq_domain_alloc,
|
|
.free = gic_irq_domain_free,
|
|
.select = gic_irq_domain_select,
|
|
};
|
|
|
|
static int partition_domain_translate(struct irq_domain *d,
|
|
struct irq_fwspec *fwspec,
|
|
unsigned long *hwirq,
|
|
unsigned int *type)
|
|
{
|
|
struct device_node *np;
|
|
int ret;
|
|
|
|
np = of_find_node_by_phandle(fwspec->param[3]);
|
|
if (WARN_ON(!np))
|
|
return -EINVAL;
|
|
|
|
ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]],
|
|
of_node_to_fwnode(np));
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
*hwirq = ret;
|
|
*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct irq_domain_ops partition_domain_ops = {
|
|
.translate = partition_domain_translate,
|
|
.select = gic_irq_domain_select,
|
|
};
|
|
|
|
static int __init gic_init_bases(void __iomem *dist_base,
|
|
struct redist_region *rdist_regs,
|
|
u32 nr_redist_regions,
|
|
u64 redist_stride,
|
|
struct fwnode_handle *handle)
|
|
{
|
|
u32 typer;
|
|
int gic_irqs;
|
|
int err;
|
|
|
|
if (!is_hyp_mode_available())
|
|
static_key_slow_dec(&supports_deactivate);
|
|
|
|
if (static_key_true(&supports_deactivate))
|
|
pr_info("GIC: Using split EOI/Deactivate mode\n");
|
|
|
|
gic_data.fwnode = handle;
|
|
gic_data.dist_base = dist_base;
|
|
gic_data.redist_regions = rdist_regs;
|
|
gic_data.nr_redist_regions = nr_redist_regions;
|
|
gic_data.redist_stride = redist_stride;
|
|
|
|
/*
|
|
* Find out how many interrupts are supported.
|
|
* The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
|
|
*/
|
|
typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
|
|
gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer);
|
|
gic_irqs = GICD_TYPER_IRQS(typer);
|
|
if (gic_irqs > 1020)
|
|
gic_irqs = 1020;
|
|
gic_data.irq_nr = gic_irqs;
|
|
|
|
gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
|
|
&gic_data);
|
|
gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
|
|
|
|
if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
|
|
err = -ENOMEM;
|
|
goto out_free;
|
|
}
|
|
|
|
set_handle_irq(gic_handle_irq);
|
|
|
|
if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
|
|
its_init(handle, &gic_data.rdists, gic_data.domain);
|
|
|
|
gic_smp_init();
|
|
gic_dist_init();
|
|
gic_cpu_init();
|
|
gic_cpu_pm_init();
|
|
|
|
return 0;
|
|
|
|
out_free:
|
|
if (gic_data.domain)
|
|
irq_domain_remove(gic_data.domain);
|
|
free_percpu(gic_data.rdists.rdist);
|
|
return err;
|
|
}
|
|
|
|
static int __init gic_validate_dist_version(void __iomem *dist_base)
|
|
{
|
|
u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
|
|
|
|
if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
|
|
return -ENODEV;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int get_cpu_number(struct device_node *dn)
|
|
{
|
|
const __be32 *cell;
|
|
u64 hwid;
|
|
int i;
|
|
|
|
cell = of_get_property(dn, "reg", NULL);
|
|
if (!cell)
|
|
return -1;
|
|
|
|
hwid = of_read_number(cell, of_n_addr_cells(dn));
|
|
|
|
/*
|
|
* Non affinity bits must be set to 0 in the DT
|
|
*/
|
|
if (hwid & ~MPIDR_HWID_BITMASK)
|
|
return -1;
|
|
|
|
for (i = 0; i < num_possible_cpus(); i++)
|
|
if (cpu_logical_map(i) == hwid)
|
|
return i;
|
|
|
|
return -1;
|
|
}
|
|
|
|
/* Create all possible partitions at boot time */
|
|
static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
|
|
{
|
|
struct device_node *parts_node, *child_part;
|
|
int part_idx = 0, i;
|
|
int nr_parts;
|
|
struct partition_affinity *parts;
|
|
|
|
parts_node = of_find_node_by_name(gic_node, "ppi-partitions");
|
|
if (!parts_node)
|
|
return;
|
|
|
|
nr_parts = of_get_child_count(parts_node);
|
|
|
|
if (!nr_parts)
|
|
return;
|
|
|
|
parts = kzalloc(sizeof(*parts) * nr_parts, GFP_KERNEL);
|
|
if (WARN_ON(!parts))
|
|
return;
|
|
|
|
for_each_child_of_node(parts_node, child_part) {
|
|
struct partition_affinity *part;
|
|
int n;
|
|
|
|
part = &parts[part_idx];
|
|
|
|
part->partition_id = of_node_to_fwnode(child_part);
|
|
|
|
pr_info("GIC: PPI partition %s[%d] { ",
|
|
child_part->name, part_idx);
|
|
|
|
n = of_property_count_elems_of_size(child_part, "affinity",
|
|
sizeof(u32));
|
|
WARN_ON(n <= 0);
|
|
|
|
for (i = 0; i < n; i++) {
|
|
int err, cpu;
|
|
u32 cpu_phandle;
|
|
struct device_node *cpu_node;
|
|
|
|
err = of_property_read_u32_index(child_part, "affinity",
|
|
i, &cpu_phandle);
|
|
if (WARN_ON(err))
|
|
continue;
|
|
|
|
cpu_node = of_find_node_by_phandle(cpu_phandle);
|
|
if (WARN_ON(!cpu_node))
|
|
continue;
|
|
|
|
cpu = get_cpu_number(cpu_node);
|
|
if (WARN_ON(cpu == -1))
|
|
continue;
|
|
|
|
pr_cont("%s[%d] ", cpu_node->full_name, cpu);
|
|
|
|
cpumask_set_cpu(cpu, &part->mask);
|
|
}
|
|
|
|
pr_cont("}\n");
|
|
part_idx++;
|
|
}
|
|
|
|
for (i = 0; i < 16; i++) {
|
|
unsigned int irq;
|
|
struct partition_desc *desc;
|
|
struct irq_fwspec ppi_fwspec = {
|
|
.fwnode = gic_data.fwnode,
|
|
.param_count = 3,
|
|
.param = {
|
|
[0] = 1,
|
|
[1] = i,
|
|
[2] = IRQ_TYPE_NONE,
|
|
},
|
|
};
|
|
|
|
irq = irq_create_fwspec_mapping(&ppi_fwspec);
|
|
if (WARN_ON(!irq))
|
|
continue;
|
|
desc = partition_create_desc(gic_data.fwnode, parts, nr_parts,
|
|
irq, &partition_domain_ops);
|
|
if (WARN_ON(!desc))
|
|
continue;
|
|
|
|
gic_data.ppi_descs[i] = desc;
|
|
}
|
|
}
|
|
|
|
static void __init gic_of_setup_kvm_info(struct device_node *node)
|
|
{
|
|
int ret;
|
|
struct resource r;
|
|
u32 gicv_idx;
|
|
|
|
gic_v3_kvm_info.type = GIC_V3;
|
|
|
|
gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
|
|
if (!gic_v3_kvm_info.maint_irq)
|
|
return;
|
|
|
|
if (of_property_read_u32(node, "#redistributor-regions",
|
|
&gicv_idx))
|
|
gicv_idx = 1;
|
|
|
|
gicv_idx += 3; /* Also skip GICD, GICC, GICH */
|
|
ret = of_address_to_resource(node, gicv_idx, &r);
|
|
if (!ret)
|
|
gic_v3_kvm_info.vcpu = r;
|
|
|
|
gic_set_kvm_info(&gic_v3_kvm_info);
|
|
}
|
|
|
|
static int __init gic_of_init(struct device_node *node, struct device_node *parent)
|
|
{
|
|
void __iomem *dist_base;
|
|
struct redist_region *rdist_regs;
|
|
u64 redist_stride;
|
|
u32 nr_redist_regions;
|
|
int err, i;
|
|
|
|
dist_base = of_iomap(node, 0);
|
|
if (!dist_base) {
|
|
pr_err("%s: unable to map gic dist registers\n",
|
|
node->full_name);
|
|
return -ENXIO;
|
|
}
|
|
|
|
err = gic_validate_dist_version(dist_base);
|
|
if (err) {
|
|
pr_err("%s: no distributor detected, giving up\n",
|
|
node->full_name);
|
|
goto out_unmap_dist;
|
|
}
|
|
|
|
if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
|
|
nr_redist_regions = 1;
|
|
|
|
rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL);
|
|
if (!rdist_regs) {
|
|
err = -ENOMEM;
|
|
goto out_unmap_dist;
|
|
}
|
|
|
|
for (i = 0; i < nr_redist_regions; i++) {
|
|
struct resource res;
|
|
int ret;
|
|
|
|
ret = of_address_to_resource(node, 1 + i, &res);
|
|
rdist_regs[i].redist_base = of_iomap(node, 1 + i);
|
|
if (ret || !rdist_regs[i].redist_base) {
|
|
pr_err("%s: couldn't map region %d\n",
|
|
node->full_name, i);
|
|
err = -ENODEV;
|
|
goto out_unmap_rdist;
|
|
}
|
|
rdist_regs[i].phys_base = res.start;
|
|
}
|
|
|
|
if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
|
|
redist_stride = 0;
|
|
|
|
err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
|
|
redist_stride, &node->fwnode);
|
|
if (err)
|
|
goto out_unmap_rdist;
|
|
|
|
gic_populate_ppi_partitions(node);
|
|
gic_of_setup_kvm_info(node);
|
|
return 0;
|
|
|
|
out_unmap_rdist:
|
|
for (i = 0; i < nr_redist_regions; i++)
|
|
if (rdist_regs[i].redist_base)
|
|
iounmap(rdist_regs[i].redist_base);
|
|
kfree(rdist_regs);
|
|
out_unmap_dist:
|
|
iounmap(dist_base);
|
|
return err;
|
|
}
|
|
|
|
IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
|
|
|
|
#ifdef CONFIG_ACPI
|
|
static struct
|
|
{
|
|
void __iomem *dist_base;
|
|
struct redist_region *redist_regs;
|
|
u32 nr_redist_regions;
|
|
bool single_redist;
|
|
u32 maint_irq;
|
|
int maint_irq_mode;
|
|
phys_addr_t vcpu_base;
|
|
} acpi_data __initdata;
|
|
|
|
static void __init
|
|
gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base)
|
|
{
|
|
static int count = 0;
|
|
|
|
acpi_data.redist_regs[count].phys_base = phys_base;
|
|
acpi_data.redist_regs[count].redist_base = redist_base;
|
|
acpi_data.redist_regs[count].single_redist = acpi_data.single_redist;
|
|
count++;
|
|
}
|
|
|
|
static int __init
|
|
gic_acpi_parse_madt_redist(struct acpi_subtable_header *header,
|
|
const unsigned long end)
|
|
{
|
|
struct acpi_madt_generic_redistributor *redist =
|
|
(struct acpi_madt_generic_redistributor *)header;
|
|
void __iomem *redist_base;
|
|
|
|
redist_base = ioremap(redist->base_address, redist->length);
|
|
if (!redist_base) {
|
|
pr_err("Couldn't map GICR region @%llx\n", redist->base_address);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
gic_acpi_register_redist(redist->base_address, redist_base);
|
|
return 0;
|
|
}
|
|
|
|
static int __init
|
|
gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header,
|
|
const unsigned long end)
|
|
{
|
|
struct acpi_madt_generic_interrupt *gicc =
|
|
(struct acpi_madt_generic_interrupt *)header;
|
|
u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
|
|
u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
|
|
void __iomem *redist_base;
|
|
|
|
redist_base = ioremap(gicc->gicr_base_address, size);
|
|
if (!redist_base)
|
|
return -ENOMEM;
|
|
|
|
gic_acpi_register_redist(gicc->gicr_base_address, redist_base);
|
|
return 0;
|
|
}
|
|
|
|
static int __init gic_acpi_collect_gicr_base(void)
|
|
{
|
|
acpi_tbl_entry_handler redist_parser;
|
|
enum acpi_madt_type type;
|
|
|
|
if (acpi_data.single_redist) {
|
|
type = ACPI_MADT_TYPE_GENERIC_INTERRUPT;
|
|
redist_parser = gic_acpi_parse_madt_gicc;
|
|
} else {
|
|
type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR;
|
|
redist_parser = gic_acpi_parse_madt_redist;
|
|
}
|
|
|
|
/* Collect redistributor base addresses in GICR entries */
|
|
if (acpi_table_parse_madt(type, redist_parser, 0) > 0)
|
|
return 0;
|
|
|
|
pr_info("No valid GICR entries exist\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header,
|
|
const unsigned long end)
|
|
{
|
|
/* Subtable presence means that redist exists, that's it */
|
|
return 0;
|
|
}
|
|
|
|
static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header,
|
|
const unsigned long end)
|
|
{
|
|
struct acpi_madt_generic_interrupt *gicc =
|
|
(struct acpi_madt_generic_interrupt *)header;
|
|
|
|
/*
|
|
* If GICC is enabled and has valid gicr base address, then it means
|
|
* GICR base is presented via GICC
|
|
*/
|
|
if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address)
|
|
return 0;
|
|
|
|
return -ENODEV;
|
|
}
|
|
|
|
static int __init gic_acpi_count_gicr_regions(void)
|
|
{
|
|
int count;
|
|
|
|
/*
|
|
* Count how many redistributor regions we have. It is not allowed
|
|
* to mix redistributor description, GICR and GICC subtables have to be
|
|
* mutually exclusive.
|
|
*/
|
|
count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
|
|
gic_acpi_match_gicr, 0);
|
|
if (count > 0) {
|
|
acpi_data.single_redist = false;
|
|
return count;
|
|
}
|
|
|
|
count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
|
|
gic_acpi_match_gicc, 0);
|
|
if (count > 0)
|
|
acpi_data.single_redist = true;
|
|
|
|
return count;
|
|
}
|
|
|
|
static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header,
|
|
struct acpi_probe_entry *ape)
|
|
{
|
|
struct acpi_madt_generic_distributor *dist;
|
|
int count;
|
|
|
|
dist = (struct acpi_madt_generic_distributor *)header;
|
|
if (dist->version != ape->driver_data)
|
|
return false;
|
|
|
|
/* We need to do that exercise anyway, the sooner the better */
|
|
count = gic_acpi_count_gicr_regions();
|
|
if (count <= 0)
|
|
return false;
|
|
|
|
acpi_data.nr_redist_regions = count;
|
|
return true;
|
|
}
|
|
|
|
static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header,
|
|
const unsigned long end)
|
|
{
|
|
struct acpi_madt_generic_interrupt *gicc =
|
|
(struct acpi_madt_generic_interrupt *)header;
|
|
int maint_irq_mode;
|
|
static int first_madt = true;
|
|
|
|
/* Skip unusable CPUs */
|
|
if (!(gicc->flags & ACPI_MADT_ENABLED))
|
|
return 0;
|
|
|
|
maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
|
|
ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
|
|
|
|
if (first_madt) {
|
|
first_madt = false;
|
|
|
|
acpi_data.maint_irq = gicc->vgic_interrupt;
|
|
acpi_data.maint_irq_mode = maint_irq_mode;
|
|
acpi_data.vcpu_base = gicc->gicv_base_address;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* The maintenance interrupt and GICV should be the same for every CPU
|
|
*/
|
|
if ((acpi_data.maint_irq != gicc->vgic_interrupt) ||
|
|
(acpi_data.maint_irq_mode != maint_irq_mode) ||
|
|
(acpi_data.vcpu_base != gicc->gicv_base_address))
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool __init gic_acpi_collect_virt_info(void)
|
|
{
|
|
int count;
|
|
|
|
count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
|
|
gic_acpi_parse_virt_madt_gicc, 0);
|
|
|
|
return (count > 0);
|
|
}
|
|
|
|
#define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
|
|
#define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
|
|
#define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
|
|
|
|
static void __init gic_acpi_setup_kvm_info(void)
|
|
{
|
|
int irq;
|
|
|
|
if (!gic_acpi_collect_virt_info()) {
|
|
pr_warn("Unable to get hardware information used for virtualization\n");
|
|
return;
|
|
}
|
|
|
|
gic_v3_kvm_info.type = GIC_V3;
|
|
|
|
irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
|
|
acpi_data.maint_irq_mode,
|
|
ACPI_ACTIVE_HIGH);
|
|
if (irq <= 0)
|
|
return;
|
|
|
|
gic_v3_kvm_info.maint_irq = irq;
|
|
|
|
if (acpi_data.vcpu_base) {
|
|
struct resource *vcpu = &gic_v3_kvm_info.vcpu;
|
|
|
|
vcpu->flags = IORESOURCE_MEM;
|
|
vcpu->start = acpi_data.vcpu_base;
|
|
vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
|
|
}
|
|
|
|
gic_set_kvm_info(&gic_v3_kvm_info);
|
|
}
|
|
|
|
static int __init
|
|
gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end)
|
|
{
|
|
struct acpi_madt_generic_distributor *dist;
|
|
struct fwnode_handle *domain_handle;
|
|
size_t size;
|
|
int i, err;
|
|
|
|
/* Get distributor base address */
|
|
dist = (struct acpi_madt_generic_distributor *)header;
|
|
acpi_data.dist_base = ioremap(dist->base_address,
|
|
ACPI_GICV3_DIST_MEM_SIZE);
|
|
if (!acpi_data.dist_base) {
|
|
pr_err("Unable to map GICD registers\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
err = gic_validate_dist_version(acpi_data.dist_base);
|
|
if (err) {
|
|
pr_err("No distributor detected at @%p, giving up",
|
|
acpi_data.dist_base);
|
|
goto out_dist_unmap;
|
|
}
|
|
|
|
size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions;
|
|
acpi_data.redist_regs = kzalloc(size, GFP_KERNEL);
|
|
if (!acpi_data.redist_regs) {
|
|
err = -ENOMEM;
|
|
goto out_dist_unmap;
|
|
}
|
|
|
|
err = gic_acpi_collect_gicr_base();
|
|
if (err)
|
|
goto out_redist_unmap;
|
|
|
|
domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base);
|
|
if (!domain_handle) {
|
|
err = -ENOMEM;
|
|
goto out_redist_unmap;
|
|
}
|
|
|
|
err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs,
|
|
acpi_data.nr_redist_regions, 0, domain_handle);
|
|
if (err)
|
|
goto out_fwhandle_free;
|
|
|
|
acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
|
|
gic_acpi_setup_kvm_info();
|
|
|
|
return 0;
|
|
|
|
out_fwhandle_free:
|
|
irq_domain_free_fwnode(domain_handle);
|
|
out_redist_unmap:
|
|
for (i = 0; i < acpi_data.nr_redist_regions; i++)
|
|
if (acpi_data.redist_regs[i].redist_base)
|
|
iounmap(acpi_data.redist_regs[i].redist_base);
|
|
kfree(acpi_data.redist_regs);
|
|
out_dist_unmap:
|
|
iounmap(acpi_data.dist_base);
|
|
return err;
|
|
}
|
|
IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
|
|
acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3,
|
|
gic_acpi_init);
|
|
IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
|
|
acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4,
|
|
gic_acpi_init);
|
|
IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
|
|
acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE,
|
|
gic_acpi_init);
|
|
#endif
|