mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-08 04:46:40 +07:00
24b35ed9a8
When the hardware is in output mode, reading the value from the hardware is not giving the correct value back. Instead read the value from the cache so we get the right value. Suggested-by: Russell King <linux@arm.linux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
427 lines
10 KiB
C
427 lines
10 KiB
C
/*
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* Support for the GPIO/IRQ expander chips present on several HTC phones.
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* These are implemented in CPLD chips present on the board.
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*
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* Copyright (c) 2007 Kevin O'Connor <kevin@koconnor.net>
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* Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
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*
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* This file may be distributed under the terms of the GNU GPL license.
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/platform_data/gpio-htc-egpio.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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struct egpio_chip {
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int reg_start;
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int cached_values;
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unsigned long is_out;
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struct device *dev;
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struct gpio_chip chip;
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};
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struct egpio_info {
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spinlock_t lock;
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/* iomem info */
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void __iomem *base_addr;
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int bus_shift; /* byte shift */
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int reg_shift; /* bit shift */
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int reg_mask;
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/* irq info */
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int ack_register;
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int ack_write;
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u16 irqs_enabled;
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uint irq_start;
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int nirqs;
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uint chained_irq;
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/* egpio info */
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struct egpio_chip *chip;
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int nchips;
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};
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static inline void egpio_writew(u16 value, struct egpio_info *ei, int reg)
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{
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writew(value, ei->base_addr + (reg << ei->bus_shift));
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}
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static inline u16 egpio_readw(struct egpio_info *ei, int reg)
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{
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return readw(ei->base_addr + (reg << ei->bus_shift));
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}
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/*
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* IRQs
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*/
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static inline void ack_irqs(struct egpio_info *ei)
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{
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egpio_writew(ei->ack_write, ei, ei->ack_register);
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pr_debug("EGPIO ack - write %x to base+%x\n",
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ei->ack_write, ei->ack_register << ei->bus_shift);
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}
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static void egpio_ack(struct irq_data *data)
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{
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}
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/* There does not appear to be a way to proactively mask interrupts
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* on the egpio chip itself. So, we simply ignore interrupts that
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* aren't desired. */
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static void egpio_mask(struct irq_data *data)
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{
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struct egpio_info *ei = irq_data_get_irq_chip_data(data);
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ei->irqs_enabled &= ~(1 << (data->irq - ei->irq_start));
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pr_debug("EGPIO mask %d %04x\n", data->irq, ei->irqs_enabled);
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}
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static void egpio_unmask(struct irq_data *data)
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{
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struct egpio_info *ei = irq_data_get_irq_chip_data(data);
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ei->irqs_enabled |= 1 << (data->irq - ei->irq_start);
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pr_debug("EGPIO unmask %d %04x\n", data->irq, ei->irqs_enabled);
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}
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static struct irq_chip egpio_muxed_chip = {
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.name = "htc-egpio",
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.irq_ack = egpio_ack,
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.irq_mask = egpio_mask,
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.irq_unmask = egpio_unmask,
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};
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static void egpio_handler(struct irq_desc *desc)
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{
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struct egpio_info *ei = irq_desc_get_handler_data(desc);
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int irqpin;
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/* Read current pins. */
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unsigned long readval = egpio_readw(ei, ei->ack_register);
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pr_debug("IRQ reg: %x\n", (unsigned int)readval);
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/* Ack/unmask interrupts. */
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ack_irqs(ei);
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/* Process all set pins. */
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readval &= ei->irqs_enabled;
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for_each_set_bit(irqpin, &readval, ei->nirqs) {
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/* Run irq handler */
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pr_debug("got IRQ %d\n", irqpin);
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generic_handle_irq(ei->irq_start + irqpin);
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}
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}
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int htc_egpio_get_wakeup_irq(struct device *dev)
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{
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struct egpio_info *ei = dev_get_drvdata(dev);
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/* Read current pins. */
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u16 readval = egpio_readw(ei, ei->ack_register);
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/* Ack/unmask interrupts. */
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ack_irqs(ei);
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/* Return first set pin. */
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readval &= ei->irqs_enabled;
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return ei->irq_start + ffs(readval) - 1;
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}
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EXPORT_SYMBOL(htc_egpio_get_wakeup_irq);
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static inline int egpio_pos(struct egpio_info *ei, int bit)
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{
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return bit >> ei->reg_shift;
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}
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static inline int egpio_bit(struct egpio_info *ei, int bit)
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{
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return 1 << (bit & ((1 << ei->reg_shift)-1));
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}
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/*
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* Input pins
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*/
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static int egpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct egpio_chip *egpio;
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struct egpio_info *ei;
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unsigned bit;
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int reg;
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int value;
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pr_debug("egpio_get_value(%d)\n", chip->base + offset);
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egpio = gpiochip_get_data(chip);
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ei = dev_get_drvdata(egpio->dev);
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bit = egpio_bit(ei, offset);
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reg = egpio->reg_start + egpio_pos(ei, offset);
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if (test_bit(offset, &egpio->is_out)) {
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return !!(egpio->cached_values & (1 << offset));
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} else {
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value = egpio_readw(ei, reg);
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pr_debug("readw(%p + %x) = %x\n",
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ei->base_addr, reg << ei->bus_shift, value);
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return !!(value & bit);
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}
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}
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static int egpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct egpio_chip *egpio;
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egpio = gpiochip_get_data(chip);
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return test_bit(offset, &egpio->is_out) ? -EINVAL : 0;
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}
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/*
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* Output pins
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*/
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static void egpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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unsigned long flag;
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struct egpio_chip *egpio;
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struct egpio_info *ei;
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unsigned bit;
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int pos;
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int reg;
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int shift;
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pr_debug("egpio_set(%s, %d(%d), %d)\n",
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chip->label, offset, offset+chip->base, value);
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egpio = gpiochip_get_data(chip);
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ei = dev_get_drvdata(egpio->dev);
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bit = egpio_bit(ei, offset);
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pos = egpio_pos(ei, offset);
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reg = egpio->reg_start + pos;
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shift = pos << ei->reg_shift;
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pr_debug("egpio %s: reg %d = 0x%04x\n", value ? "set" : "clear",
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reg, (egpio->cached_values >> shift) & ei->reg_mask);
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spin_lock_irqsave(&ei->lock, flag);
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if (value)
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egpio->cached_values |= (1 << offset);
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else
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egpio->cached_values &= ~(1 << offset);
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egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg);
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spin_unlock_irqrestore(&ei->lock, flag);
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}
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static int egpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct egpio_chip *egpio;
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egpio = gpiochip_get_data(chip);
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if (test_bit(offset, &egpio->is_out)) {
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egpio_set(chip, offset, value);
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return 0;
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} else {
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return -EINVAL;
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}
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}
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static int egpio_get_direction(struct gpio_chip *chip, unsigned offset)
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{
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struct egpio_chip *egpio;
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egpio = gpiochip_get_data(chip);
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return !test_bit(offset, &egpio->is_out);
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}
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static void egpio_write_cache(struct egpio_info *ei)
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{
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int i;
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struct egpio_chip *egpio;
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int shift;
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for (i = 0; i < ei->nchips; i++) {
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egpio = &(ei->chip[i]);
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if (!egpio->is_out)
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continue;
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for (shift = 0; shift < egpio->chip.ngpio;
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shift += (1<<ei->reg_shift)) {
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int reg = egpio->reg_start + egpio_pos(ei, shift);
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if (!((egpio->is_out >> shift) & ei->reg_mask))
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continue;
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pr_debug("EGPIO: setting %x to %x, was %x\n", reg,
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(egpio->cached_values >> shift) & ei->reg_mask,
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egpio_readw(ei, reg));
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egpio_writew((egpio->cached_values >> shift)
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& ei->reg_mask, ei, reg);
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}
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}
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}
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/*
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* Setup
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*/
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static int __init egpio_probe(struct platform_device *pdev)
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{
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struct htc_egpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
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struct resource *res;
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struct egpio_info *ei;
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struct gpio_chip *chip;
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unsigned int irq, irq_end;
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int i;
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int ret;
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/* Initialize ei data structure. */
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ei = devm_kzalloc(&pdev->dev, sizeof(*ei), GFP_KERNEL);
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if (!ei)
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return -ENOMEM;
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spin_lock_init(&ei->lock);
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/* Find chained irq */
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ret = -EINVAL;
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res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (res)
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ei->chained_irq = res->start;
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/* Map egpio chip into virtual address space. */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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goto fail;
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ei->base_addr = devm_ioremap_nocache(&pdev->dev, res->start,
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resource_size(res));
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if (!ei->base_addr)
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goto fail;
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pr_debug("EGPIO phys=%08x virt=%p\n", (u32)res->start, ei->base_addr);
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if ((pdata->bus_width != 16) && (pdata->bus_width != 32))
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goto fail;
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ei->bus_shift = fls(pdata->bus_width - 1) - 3;
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pr_debug("bus_shift = %d\n", ei->bus_shift);
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if ((pdata->reg_width != 8) && (pdata->reg_width != 16))
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goto fail;
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ei->reg_shift = fls(pdata->reg_width - 1);
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pr_debug("reg_shift = %d\n", ei->reg_shift);
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ei->reg_mask = (1 << pdata->reg_width) - 1;
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platform_set_drvdata(pdev, ei);
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ei->nchips = pdata->num_chips;
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ei->chip = devm_kzalloc(&pdev->dev,
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sizeof(struct egpio_chip) * ei->nchips,
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GFP_KERNEL);
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if (!ei->chip) {
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ret = -ENOMEM;
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goto fail;
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}
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for (i = 0; i < ei->nchips; i++) {
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ei->chip[i].reg_start = pdata->chip[i].reg_start;
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ei->chip[i].cached_values = pdata->chip[i].initial_values;
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ei->chip[i].is_out = pdata->chip[i].direction;
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ei->chip[i].dev = &(pdev->dev);
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chip = &(ei->chip[i].chip);
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chip->label = "htc-egpio";
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chip->parent = &pdev->dev;
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chip->owner = THIS_MODULE;
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chip->get = egpio_get;
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chip->set = egpio_set;
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chip->direction_input = egpio_direction_input;
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chip->direction_output = egpio_direction_output;
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chip->get_direction = egpio_get_direction;
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chip->base = pdata->chip[i].gpio_base;
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chip->ngpio = pdata->chip[i].num_gpios;
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gpiochip_add_data(chip, &ei->chip[i]);
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}
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/* Set initial pin values */
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egpio_write_cache(ei);
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ei->irq_start = pdata->irq_base;
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ei->nirqs = pdata->num_irqs;
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ei->ack_register = pdata->ack_register;
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if (ei->chained_irq) {
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/* Setup irq handlers */
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ei->ack_write = 0xFFFF;
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if (pdata->invert_acks)
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ei->ack_write = 0;
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irq_end = ei->irq_start + ei->nirqs;
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for (irq = ei->irq_start; irq < irq_end; irq++) {
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irq_set_chip_and_handler(irq, &egpio_muxed_chip,
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handle_simple_irq);
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irq_set_chip_data(irq, ei);
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irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
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}
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irq_set_irq_type(ei->chained_irq, IRQ_TYPE_EDGE_RISING);
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irq_set_chained_handler_and_data(ei->chained_irq,
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egpio_handler, ei);
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ack_irqs(ei);
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device_init_wakeup(&pdev->dev, 1);
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}
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return 0;
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fail:
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printk(KERN_ERR "EGPIO failed to setup\n");
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return ret;
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}
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#ifdef CONFIG_PM
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static int egpio_suspend(struct platform_device *pdev, pm_message_t state)
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{
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struct egpio_info *ei = platform_get_drvdata(pdev);
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if (ei->chained_irq && device_may_wakeup(&pdev->dev))
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enable_irq_wake(ei->chained_irq);
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return 0;
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}
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static int egpio_resume(struct platform_device *pdev)
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{
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struct egpio_info *ei = platform_get_drvdata(pdev);
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if (ei->chained_irq && device_may_wakeup(&pdev->dev))
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disable_irq_wake(ei->chained_irq);
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/* Update registers from the cache, in case
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the CPLD was powered off during suspend */
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egpio_write_cache(ei);
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return 0;
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}
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#else
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#define egpio_suspend NULL
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#define egpio_resume NULL
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#endif
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static struct platform_driver egpio_driver = {
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.driver = {
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.name = "htc-egpio",
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.suppress_bind_attrs = true,
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},
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.suspend = egpio_suspend,
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.resume = egpio_resume,
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};
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static int __init egpio_init(void)
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{
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return platform_driver_probe(&egpio_driver, egpio_probe);
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}
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/* start early for dependencies */
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subsys_initcall(egpio_init);
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