mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-11 00:46:38 +07:00
3ddc76dfc7
Pull timer type cleanups from Thomas Gleixner: "This series does a tree wide cleanup of types related to timers/timekeeping. - Get rid of cycles_t and use a plain u64. The type is not really helpful and caused more confusion than clarity - Get rid of the ktime union. The union has become useless as we use the scalar nanoseconds storage unconditionally now. The 32bit timespec alike storage got removed due to the Y2038 limitations some time ago. That leaves the odd union access around for no reason. Clean it up. Both changes have been done with coccinelle and a small amount of manual mopping up" * 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: ktime: Get rid of ktime_equal() ktime: Cleanup ktime_set() usage ktime: Get rid of the union clocksource: Use a plain u64 instead of cycle_t
250 lines
6.5 KiB
C
250 lines
6.5 KiB
C
/*
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* J-Core SoC PIT/clocksource driver
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*
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* Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/sched_clock.h>
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#include <linux/cpu.h>
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#include <linux/cpuhotplug.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define PIT_IRQ_SHIFT 12
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#define PIT_PRIO_SHIFT 20
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#define PIT_ENABLE_SHIFT 26
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#define PIT_PRIO_MASK 0xf
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#define REG_PITEN 0x00
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#define REG_THROT 0x10
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#define REG_COUNT 0x14
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#define REG_BUSPD 0x18
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#define REG_SECHI 0x20
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#define REG_SECLO 0x24
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#define REG_NSEC 0x28
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struct jcore_pit {
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struct clock_event_device ced;
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void __iomem *base;
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unsigned long periodic_delta;
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u32 enable_val;
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};
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static void __iomem *jcore_pit_base;
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static struct jcore_pit __percpu *jcore_pit_percpu;
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static notrace u64 jcore_sched_clock_read(void)
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{
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u32 seclo, nsec, seclo0;
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__iomem void *base = jcore_pit_base;
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seclo = readl(base + REG_SECLO);
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do {
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seclo0 = seclo;
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nsec = readl(base + REG_NSEC);
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seclo = readl(base + REG_SECLO);
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} while (seclo0 != seclo);
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return seclo * NSEC_PER_SEC + nsec;
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}
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static u64 jcore_clocksource_read(struct clocksource *cs)
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{
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return jcore_sched_clock_read();
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}
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static int jcore_pit_disable(struct jcore_pit *pit)
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{
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writel(0, pit->base + REG_PITEN);
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return 0;
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}
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static int jcore_pit_set(unsigned long delta, struct jcore_pit *pit)
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{
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jcore_pit_disable(pit);
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writel(delta, pit->base + REG_THROT);
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writel(pit->enable_val, pit->base + REG_PITEN);
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return 0;
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}
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static int jcore_pit_set_state_shutdown(struct clock_event_device *ced)
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{
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struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
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return jcore_pit_disable(pit);
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}
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static int jcore_pit_set_state_oneshot(struct clock_event_device *ced)
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{
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struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
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return jcore_pit_disable(pit);
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}
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static int jcore_pit_set_state_periodic(struct clock_event_device *ced)
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{
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struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
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return jcore_pit_set(pit->periodic_delta, pit);
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}
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static int jcore_pit_set_next_event(unsigned long delta,
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struct clock_event_device *ced)
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{
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struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
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return jcore_pit_set(delta, pit);
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}
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static int jcore_pit_local_init(unsigned cpu)
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{
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struct jcore_pit *pit = this_cpu_ptr(jcore_pit_percpu);
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unsigned buspd, freq;
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pr_info("Local J-Core PIT init on cpu %u\n", cpu);
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buspd = readl(pit->base + REG_BUSPD);
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freq = DIV_ROUND_CLOSEST(NSEC_PER_SEC, buspd);
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pit->periodic_delta = DIV_ROUND_CLOSEST(NSEC_PER_SEC, HZ * buspd);
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clockevents_config_and_register(&pit->ced, freq, 1, ULONG_MAX);
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return 0;
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}
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static irqreturn_t jcore_timer_interrupt(int irq, void *dev_id)
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{
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struct jcore_pit *pit = this_cpu_ptr(dev_id);
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if (clockevent_state_oneshot(&pit->ced))
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jcore_pit_disable(pit);
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pit->ced.event_handler(&pit->ced);
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return IRQ_HANDLED;
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}
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static int __init jcore_pit_init(struct device_node *node)
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{
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int err;
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unsigned pit_irq, cpu;
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unsigned long hwirq;
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u32 irqprio, enable_val;
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jcore_pit_base = of_iomap(node, 0);
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if (!jcore_pit_base) {
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pr_err("Error: Cannot map base address for J-Core PIT\n");
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return -ENXIO;
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}
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pit_irq = irq_of_parse_and_map(node, 0);
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if (!pit_irq) {
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pr_err("Error: J-Core PIT has no IRQ\n");
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return -ENXIO;
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}
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pr_info("Initializing J-Core PIT at %p IRQ %d\n",
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jcore_pit_base, pit_irq);
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err = clocksource_mmio_init(jcore_pit_base, "jcore_pit_cs",
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NSEC_PER_SEC, 400, 32,
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jcore_clocksource_read);
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if (err) {
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pr_err("Error registering clocksource device: %d\n", err);
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return err;
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}
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sched_clock_register(jcore_sched_clock_read, 32, NSEC_PER_SEC);
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jcore_pit_percpu = alloc_percpu(struct jcore_pit);
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if (!jcore_pit_percpu) {
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pr_err("Failed to allocate memory for clock event device\n");
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return -ENOMEM;
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}
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err = request_irq(pit_irq, jcore_timer_interrupt,
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IRQF_TIMER | IRQF_PERCPU,
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"jcore_pit", jcore_pit_percpu);
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if (err) {
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pr_err("pit irq request failed: %d\n", err);
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free_percpu(jcore_pit_percpu);
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return err;
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}
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/*
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* The J-Core PIT is not hard-wired to a particular IRQ, but
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* integrated with the interrupt controller such that the IRQ it
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* generates is programmable, as follows:
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*
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* The bit layout of the PIT enable register is:
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*
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* .....e..ppppiiiiiiii............
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*
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* where the .'s indicate unrelated/unused bits, e is enable,
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* p is priority, and i is hard irq number.
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*
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* For the PIT included in AIC1 (obsolete but still in use),
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* any hard irq (trap number) can be programmed via the 8
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* iiiiiiii bits, and a priority (0-15) is programmable
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* separately in the pppp bits.
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*
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* For the PIT included in AIC2 (current), the programming
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* interface is equivalent modulo interrupt mapping. This is
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* why a different compatible tag was not used. However only
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* traps 64-127 (the ones actually intended to be used for
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* interrupts, rather than syscalls/exceptions/etc.) can be
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* programmed (the high 2 bits of i are ignored) and the
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* priority pppp is <<2'd and or'd onto the irq number. This
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* choice seems to have been made on the hardware engineering
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* side under an assumption that preserving old AIC1 priority
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* mappings was important. Future models will likely ignore
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* the pppp field.
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*/
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hwirq = irq_get_irq_data(pit_irq)->hwirq;
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irqprio = (hwirq >> 2) & PIT_PRIO_MASK;
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enable_val = (1U << PIT_ENABLE_SHIFT)
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| (hwirq << PIT_IRQ_SHIFT)
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| (irqprio << PIT_PRIO_SHIFT);
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for_each_present_cpu(cpu) {
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struct jcore_pit *pit = per_cpu_ptr(jcore_pit_percpu, cpu);
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pit->base = of_iomap(node, cpu);
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if (!pit->base) {
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pr_err("Unable to map PIT for cpu %u\n", cpu);
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continue;
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}
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pit->ced.name = "jcore_pit";
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pit->ced.features = CLOCK_EVT_FEAT_PERIODIC
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| CLOCK_EVT_FEAT_ONESHOT
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| CLOCK_EVT_FEAT_PERCPU;
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pit->ced.cpumask = cpumask_of(cpu);
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pit->ced.rating = 400;
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pit->ced.irq = pit_irq;
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pit->ced.set_state_shutdown = jcore_pit_set_state_shutdown;
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pit->ced.set_state_periodic = jcore_pit_set_state_periodic;
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pit->ced.set_state_oneshot = jcore_pit_set_state_oneshot;
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pit->ced.set_next_event = jcore_pit_set_next_event;
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pit->enable_val = enable_val;
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}
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cpuhp_setup_state(CPUHP_AP_JCORE_TIMER_STARTING,
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"clockevents/jcore:starting",
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jcore_pit_local_init, NULL);
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return 0;
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}
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CLOCKSOURCE_OF_DECLARE(jcore_pit, "jcore,pit", jcore_pit_init);
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