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PQR_ASSOC MSR contains the RMID used for preformance monitoring of cache occupancy and memory bandwidth. The upper 32bit of this MSR contain the CLOSID for cache allocation. So we need to share the information between the two facilities. Move the rdt data structure declaration into the shared header file and make the per cpu data structure containing the MSR values global. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Cc: "Ravi V Shankar" <ravi.v.shankar@intel.com> Cc: "Tony Luck" <tony.luck@intel.com> Cc: "David Carrillo-Cisneros" <davidcc@google.com> Cc: "Sai Prakhya" <sai.praneeth.prakhya@intel.com> Cc: "Peter Zijlstra" <peterz@infradead.org> Cc: "Stephane Eranian" <eranian@google.com> Cc: "Dave Hansen" <dave.hansen@intel.com> Cc: "Shaohua Li" <shli@fb.com> Cc: "Nilay Vaish" <nilayvaish@gmail.com> Cc: "Vikas Shivappa" <vikas.shivappa@linux.intel.com> Cc: "Ingo Molnar" <mingo@elte.hu> Cc: "Borislav Petkov" <bp@suse.de> Cc: "H. Peter Anvin" <h.peter.anvin@intel.com> Link: http://lkml.kernel.org/r/1477142405-32078-10-git-send-email-fenghua.yu@intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
28 lines
745 B
C
28 lines
745 B
C
#ifndef _ASM_X86_INTEL_RDT_COMMON_H
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#define _ASM_X86_INTEL_RDT_COMMON_H
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#define MSR_IA32_PQR_ASSOC 0x0c8f
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/**
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* struct intel_pqr_state - State cache for the PQR MSR
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* @rmid: The cached Resource Monitoring ID
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* @closid: The cached Class Of Service ID
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* @rmid_usecnt: The usage counter for rmid
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*
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* The upper 32 bits of MSR_IA32_PQR_ASSOC contain closid and the
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* lower 10 bits rmid. The update to MSR_IA32_PQR_ASSOC always
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* contains both parts, so we need to cache them.
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*
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* The cache also helps to avoid pointless updates if the value does
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* not change.
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*/
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struct intel_pqr_state {
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u32 rmid;
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u32 closid;
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int rmid_usecnt;
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};
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DECLARE_PER_CPU(struct intel_pqr_state, pqr_state);
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#endif /* _ASM_X86_INTEL_RDT_COMMON_H */
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