linux_dsm_epyc7002/drivers/gpu
Durgadoss R 44395bfe2f drm/i915: Enable eDP DRRS for CHV
This patch enables eDP DRRS for CHV by adding the
required IS_CHERRYVIEW() checks.
CHV uses the same register bit as VLV.

[Vandana]: Since CHV has 2 sets of M_N registers, it will follow the same code
path as gen < 8. Added CHV check in dp_set_m_n()

[Ram]: Rebased on top of previous patch modifications

Signed-off-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-02-24 11:51:38 +01:00
..
drm drm/i915: Enable eDP DRRS for CHV 2015-02-24 11:51:38 +01:00
host1x gpu: host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 register 2014-11-13 16:11:57 +01:00
ipu-v3 gpu: ipu-di: Switch to DIV_ROUND_CLOSEST for DI clock divider calc 2015-01-07 19:15:04 +01:00
vga
Makefile