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The Cadence MIPI-CSI2 TX controller is a CSI2 bridge that supports up to 4 video streams and can output on up to 4 CSI-2 lanes, depending on the hardware implementation. It can operate with an external D-PHY, an internal one or no D-PHY at all in some configurations. Acked-by: Benoit Parrot <bparrot@ti.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
99 lines
2.4 KiB
Plaintext
99 lines
2.4 KiB
Plaintext
Cadence MIPI-CSI2 TX controller
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===============================
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The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
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4 CSI lanes in output, and up to 4 different pixel streams in input.
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Required properties:
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- compatible: must be set to "cdns,csi2tx"
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- reg: base address and size of the memory mapped region
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- clocks: phandles to the clocks driving the controller
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- clock-names: must contain:
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* esc_clk: escape mode clock
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* p_clk: register bank clock
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* pixel_if[0-3]_clk: pixel stream output clock, one for each stream
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implemented in hardware, between 0 and 3
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Optional properties
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- phys: phandle to the D-PHY. If it is set, phy-names need to be set
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- phy-names: must contain "dphy"
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Required subnodes:
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- ports: A ports node with one port child node per device input and output
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port, in accordance with the video interface bindings defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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port nodes are numbered as follows.
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Port Description
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-----------------------------
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0 CSI-2 output
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1 Stream 0 input
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2 Stream 1 input
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3 Stream 2 input
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4 Stream 3 input
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The stream input port nodes are optional if they are not
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connected to anything at the hardware level or implemented
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in the design. Since there is only one endpoint per port,
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the endpoints are not numbered.
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Example:
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csi2tx: csi-bridge@0d0e1000 {
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compatible = "cdns,csi2tx";
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reg = <0x0d0e1000 0x1000>;
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clocks = <&byteclock>, <&byteclock>,
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<&coreclock>, <&coreclock>,
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<&coreclock>, <&coreclock>;
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clock-names = "p_clk", "esc_clk",
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"pixel_if0_clk", "pixel_if1_clk",
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"pixel_if2_clk", "pixel_if3_clk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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csi2tx_out: endpoint {
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remote-endpoint = <&remote_in>;
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clock-lanes = <0>;
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data-lanes = <1 2>;
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};
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};
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port@1 {
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reg = <1>;
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csi2tx_in_stream0: endpoint {
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remote-endpoint = <&stream0_out>;
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};
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};
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port@2 {
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reg = <2>;
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csi2tx_in_stream1: endpoint {
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remote-endpoint = <&stream1_out>;
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};
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};
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port@3 {
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reg = <3>;
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csi2tx_in_stream2: endpoint {
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remote-endpoint = <&stream2_out>;
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};
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};
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port@4 {
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reg = <4>;
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csi2tx_in_stream3: endpoint {
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remote-endpoint = <&stream3_out>;
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};
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};
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};
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};
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