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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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441f199a37
The Tegra clock driver is initialized during the ARM machine descriptor's .init_irq() hook. It can't be initialized earlier, since dynamic memory usage is required. It can't be initialized later, since the .init_timer() hook needs the clocks initialized. However, at this time, udelay() doesn't work. The Tegra clock initialization table may enable some PLLs. Enabling a PLL may require usage of udelay(). Hence, this can't happen right when the clock driver is initialized. To solve this, separate the clock driver initialization from the clock table processing, so they can execute at separate times. Signed-off-by: Stephen Warren <swarren@nvidia.com>
96 lines
2.4 KiB
C
96 lines
2.4 KiB
C
/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/clk/tegra.h>
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#include "clk.h"
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/* Global data of Tegra CPU CAR ops */
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struct tegra_cpu_car_ops *tegra_cpu_car_ops;
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void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
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struct clk *clks[], int clk_max)
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{
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struct clk *clk;
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for (; dup_list->clk_id < clk_max; dup_list++) {
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clk = clks[dup_list->clk_id];
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dup_list->lookup.clk = clk;
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clkdev_add(&dup_list->lookup);
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}
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}
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void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
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struct clk *clks[], int clk_max)
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{
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struct clk *clk;
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for (; tbl->clk_id < clk_max; tbl++) {
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clk = clks[tbl->clk_id];
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if (IS_ERR_OR_NULL(clk))
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return;
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if (tbl->parent_id < clk_max) {
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struct clk *parent = clks[tbl->parent_id];
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if (clk_set_parent(clk, parent)) {
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pr_err("%s: Failed to set parent %s of %s\n",
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__func__, __clk_get_name(parent),
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__clk_get_name(clk));
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WARN_ON(1);
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}
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}
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if (tbl->rate)
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if (clk_set_rate(clk, tbl->rate)) {
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pr_err("%s: Failed to set rate %lu of %s\n",
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__func__, tbl->rate,
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__clk_get_name(clk));
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WARN_ON(1);
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}
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if (tbl->state)
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if (clk_prepare_enable(clk)) {
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pr_err("%s: Failed to enable %s\n", __func__,
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__clk_get_name(clk));
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WARN_ON(1);
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}
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}
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}
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static const struct of_device_id tegra_dt_clk_match[] = {
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{ .compatible = "nvidia,tegra20-car", .data = tegra20_clock_init },
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{ .compatible = "nvidia,tegra30-car", .data = tegra30_clock_init },
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{ }
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};
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void __init tegra_clocks_init(void)
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{
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of_clk_init(tegra_dt_clk_match);
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}
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tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
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void __init tegra_clocks_apply_init_table(void)
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{
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if (!tegra_clk_apply_init_table)
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return;
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tegra_clk_apply_init_table();
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}
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