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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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af0bd4e9ba
The Allwinner A20 has an ethernet controller that seems to be an early version of Synopsys DesignWare MAC 10/100/1000 Universal, which is supported by the stmmac driver. Allwinner's GMAC requires setting additional registers in the SoC's clock control unit. The exact version of the DWMAC IP that Allwinner uses is unknown, thus the exact feature set is unknown. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: David S. Miller <davem@davemloft.net>
141 lines
3.5 KiB
C
141 lines
3.5 KiB
C
/**
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* dwmac-sunxi.c - Allwinner sunxi DWMAC specific glue layer
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*
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* Copyright (C) 2013 Chen-Yu Tsai
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*
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* Chen-Yu Tsai <wens@csie.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/stmmac.h>
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#include <linux/clk.h>
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#include <linux/phy.h>
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#include <linux/of_net.h>
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#include <linux/regulator/consumer.h>
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struct sunxi_priv_data {
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int interface;
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int clk_enabled;
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struct clk *tx_clk;
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struct regulator *regulator;
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};
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static void *sun7i_gmac_setup(struct platform_device *pdev)
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{
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struct sunxi_priv_data *gmac;
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struct device *dev = &pdev->dev;
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gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
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if (!gmac)
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return ERR_PTR(-ENOMEM);
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gmac->interface = of_get_phy_mode(dev->of_node);
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gmac->tx_clk = devm_clk_get(dev, "allwinner_gmac_tx");
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if (IS_ERR(gmac->tx_clk)) {
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dev_err(dev, "could not get tx clock\n");
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return gmac->tx_clk;
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}
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/* Optional regulator for PHY */
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gmac->regulator = devm_regulator_get_optional(dev, "phy");
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if (IS_ERR(gmac->regulator)) {
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if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER)
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return ERR_PTR(-EPROBE_DEFER);
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dev_info(dev, "no regulator found\n");
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gmac->regulator = NULL;
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}
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return gmac;
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}
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#define SUN7I_GMAC_GMII_RGMII_RATE 125000000
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#define SUN7I_GMAC_MII_RATE 25000000
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static int sun7i_gmac_init(struct platform_device *pdev, void *priv)
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{
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struct sunxi_priv_data *gmac = priv;
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int ret;
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if (gmac->regulator) {
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ret = regulator_enable(gmac->regulator);
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if (ret)
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return ret;
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}
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/* Set GMAC interface port mode
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*
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* The GMAC TX clock lines are configured by setting the clock
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* rate, which then uses the auto-reparenting feature of the
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* clock driver, and enabling/disabling the clock.
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*/
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if (gmac->interface == PHY_INTERFACE_MODE_RGMII) {
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clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE);
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clk_prepare_enable(gmac->tx_clk);
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gmac->clk_enabled = 1;
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} else {
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clk_set_rate(gmac->tx_clk, SUN7I_GMAC_MII_RATE);
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clk_prepare(gmac->tx_clk);
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}
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return 0;
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}
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static void sun7i_gmac_exit(struct platform_device *pdev, void *priv)
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{
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struct sunxi_priv_data *gmac = priv;
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if (gmac->clk_enabled) {
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clk_disable(gmac->tx_clk);
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gmac->clk_enabled = 0;
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}
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clk_unprepare(gmac->tx_clk);
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if (gmac->regulator)
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regulator_disable(gmac->regulator);
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}
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static void sun7i_fix_speed(void *priv, unsigned int speed)
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{
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struct sunxi_priv_data *gmac = priv;
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/* only GMII mode requires us to reconfigure the clock lines */
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if (gmac->interface != PHY_INTERFACE_MODE_GMII)
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return;
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if (gmac->clk_enabled) {
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clk_disable(gmac->tx_clk);
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gmac->clk_enabled = 0;
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}
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clk_unprepare(gmac->tx_clk);
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if (speed == 1000) {
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clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE);
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clk_prepare_enable(gmac->tx_clk);
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gmac->clk_enabled = 1;
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} else {
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clk_set_rate(gmac->tx_clk, SUN7I_GMAC_MII_RATE);
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clk_prepare(gmac->tx_clk);
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}
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}
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/* of_data specifying hardware features and callbacks.
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* hardware features were copied from Allwinner drivers. */
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const struct stmmac_of_data sun7i_gmac_data = {
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.has_gmac = 1,
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.tx_coe = 1,
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.fix_mac_speed = sun7i_fix_speed,
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.setup = sun7i_gmac_setup,
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.init = sun7i_gmac_init,
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.exit = sun7i_gmac_exit,
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};
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