mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b24413180f
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
304 lines
8.5 KiB
C
304 lines
8.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_PERF_EVENT_H
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#define _ASM_X86_PERF_EVENT_H
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/*
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* Performance event hw details:
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*/
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#define INTEL_PMC_MAX_GENERIC 32
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#define INTEL_PMC_MAX_FIXED 3
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#define INTEL_PMC_IDX_FIXED 32
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#define X86_PMC_IDX_MAX 64
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#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
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#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
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#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
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#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
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#define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL
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#define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL
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#define ARCH_PERFMON_EVENTSEL_USR (1ULL << 16)
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#define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17)
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#define ARCH_PERFMON_EVENTSEL_EDGE (1ULL << 18)
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#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL (1ULL << 19)
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#define ARCH_PERFMON_EVENTSEL_INT (1ULL << 20)
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#define ARCH_PERFMON_EVENTSEL_ANY (1ULL << 21)
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#define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22)
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#define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23)
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#define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
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#define HSW_IN_TX (1ULL << 32)
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#define HSW_IN_TX_CHECKPOINTED (1ULL << 33)
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#define AMD64_EVENTSEL_INT_CORE_ENABLE (1ULL << 36)
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#define AMD64_EVENTSEL_GUESTONLY (1ULL << 40)
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#define AMD64_EVENTSEL_HOSTONLY (1ULL << 41)
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#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT 37
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#define AMD64_EVENTSEL_INT_CORE_SEL_MASK \
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(0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
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#define AMD64_EVENTSEL_EVENT \
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(ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
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#define INTEL_ARCH_EVENT_MASK \
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(ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)
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#define X86_RAW_EVENT_MASK \
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(ARCH_PERFMON_EVENTSEL_EVENT | \
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ARCH_PERFMON_EVENTSEL_UMASK | \
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ARCH_PERFMON_EVENTSEL_EDGE | \
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ARCH_PERFMON_EVENTSEL_INV | \
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ARCH_PERFMON_EVENTSEL_CMASK)
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#define X86_ALL_EVENT_FLAGS \
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(ARCH_PERFMON_EVENTSEL_EDGE | \
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ARCH_PERFMON_EVENTSEL_INV | \
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ARCH_PERFMON_EVENTSEL_CMASK | \
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ARCH_PERFMON_EVENTSEL_ANY | \
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ARCH_PERFMON_EVENTSEL_PIN_CONTROL | \
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HSW_IN_TX | \
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HSW_IN_TX_CHECKPOINTED)
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#define AMD64_RAW_EVENT_MASK \
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(X86_RAW_EVENT_MASK | \
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AMD64_EVENTSEL_EVENT)
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#define AMD64_RAW_EVENT_MASK_NB \
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(AMD64_EVENTSEL_EVENT | \
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ARCH_PERFMON_EVENTSEL_UMASK)
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#define AMD64_NUM_COUNTERS 4
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#define AMD64_NUM_COUNTERS_CORE 6
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#define AMD64_NUM_COUNTERS_NB 4
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
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(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
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#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
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#define ARCH_PERFMON_EVENTS_COUNT 7
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/*
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* Intel "Architectural Performance Monitoring" CPUID
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* detection/enumeration details:
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*/
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union cpuid10_eax {
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struct {
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unsigned int version_id:8;
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unsigned int num_counters:8;
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unsigned int bit_width:8;
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unsigned int mask_length:8;
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} split;
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unsigned int full;
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};
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union cpuid10_ebx {
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struct {
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unsigned int no_unhalted_core_cycles:1;
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unsigned int no_instructions_retired:1;
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unsigned int no_unhalted_reference_cycles:1;
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unsigned int no_llc_reference:1;
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unsigned int no_llc_misses:1;
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unsigned int no_branch_instruction_retired:1;
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unsigned int no_branch_misses_retired:1;
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} split;
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unsigned int full;
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};
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union cpuid10_edx {
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struct {
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unsigned int num_counters_fixed:5;
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unsigned int bit_width_fixed:8;
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unsigned int reserved:19;
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} split;
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unsigned int full;
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};
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struct x86_pmu_capability {
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int version;
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int num_counters_gp;
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int num_counters_fixed;
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int bit_width_gp;
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int bit_width_fixed;
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unsigned int events_mask;
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int events_mask_len;
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};
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/*
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* Fixed-purpose performance events:
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*/
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/*
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* All 3 fixed-mode PMCs are configured via this single MSR:
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*/
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#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
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/*
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* The counts are available in three separate MSRs:
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*/
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/* Instr_Retired.Any: */
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#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
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#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0)
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/* CPU_CLK_Unhalted.Core: */
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#define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
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#define INTEL_PMC_IDX_FIXED_CPU_CYCLES (INTEL_PMC_IDX_FIXED + 1)
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/* CPU_CLK_Unhalted.Ref: */
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#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
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#define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2)
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#define INTEL_PMC_MSK_FIXED_REF_CYCLES (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)
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/*
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* We model BTS tracing as another fixed-mode PMC.
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*
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* We choose a value in the middle of the fixed event range, since lower
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* values are used by actual fixed events and higher values are used
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* to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
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*/
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#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 16)
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#define GLOBAL_STATUS_COND_CHG BIT_ULL(63)
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#define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(62)
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#define GLOBAL_STATUS_UNC_OVF BIT_ULL(61)
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#define GLOBAL_STATUS_ASIF BIT_ULL(60)
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#define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59)
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#define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(58)
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#define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(55)
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/*
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* IBS cpuid feature detection
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*/
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#define IBS_CPUID_FEATURES 0x8000001b
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/*
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* Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
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* bit 0 is used to indicate the existence of IBS.
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*/
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#define IBS_CAPS_AVAIL (1U<<0)
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#define IBS_CAPS_FETCHSAM (1U<<1)
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#define IBS_CAPS_OPSAM (1U<<2)
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#define IBS_CAPS_RDWROPCNT (1U<<3)
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#define IBS_CAPS_OPCNT (1U<<4)
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#define IBS_CAPS_BRNTRGT (1U<<5)
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#define IBS_CAPS_OPCNTEXT (1U<<6)
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#define IBS_CAPS_RIPINVALIDCHK (1U<<7)
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#define IBS_CAPS_OPBRNFUSE (1U<<8)
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#define IBS_CAPS_FETCHCTLEXTD (1U<<9)
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#define IBS_CAPS_OPDATA4 (1U<<10)
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#define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \
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| IBS_CAPS_FETCHSAM \
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| IBS_CAPS_OPSAM)
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/*
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* IBS APIC setup
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*/
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#define IBSCTL 0x1cc
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#define IBSCTL_LVT_OFFSET_VALID (1ULL<<8)
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#define IBSCTL_LVT_OFFSET_MASK 0x0F
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/* ibs fetch bits/masks */
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#define IBS_FETCH_RAND_EN (1ULL<<57)
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#define IBS_FETCH_VAL (1ULL<<49)
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#define IBS_FETCH_ENABLE (1ULL<<48)
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#define IBS_FETCH_CNT 0xFFFF0000ULL
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#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
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/* ibs op bits/masks */
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/* lower 4 bits of the current count are ignored: */
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#define IBS_OP_CUR_CNT (0xFFFF0ULL<<32)
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#define IBS_OP_CNT_CTL (1ULL<<19)
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#define IBS_OP_VAL (1ULL<<18)
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#define IBS_OP_ENABLE (1ULL<<17)
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#define IBS_OP_MAX_CNT 0x0000FFFFULL
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#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */
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#define IBS_RIP_INVALID (1ULL<<38)
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#ifdef CONFIG_X86_LOCAL_APIC
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extern u32 get_ibs_caps(void);
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#else
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static inline u32 get_ibs_caps(void) { return 0; }
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#endif
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#ifdef CONFIG_PERF_EVENTS
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extern void perf_events_lapic_init(void);
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/*
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* Abuse bits {3,5} of the cpu eflags register. These flags are otherwise
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* unused and ABI specified to be 0, so nobody should care what we do with
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* them.
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*
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* EXACT - the IP points to the exact instruction that triggered the
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* event (HW bugs exempt).
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* VM - original X86_VM_MASK; see set_linear_ip().
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*/
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#define PERF_EFLAGS_EXACT (1UL << 3)
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#define PERF_EFLAGS_VM (1UL << 5)
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struct pt_regs;
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extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
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extern unsigned long perf_misc_flags(struct pt_regs *regs);
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#define perf_misc_flags(regs) perf_misc_flags(regs)
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#include <asm/stacktrace.h>
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/*
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* We abuse bit 3 from flags to pass exact information, see perf_misc_flags
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* and the comment with PERF_EFLAGS_EXACT.
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*/
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#define perf_arch_fetch_caller_regs(regs, __ip) { \
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(regs)->ip = (__ip); \
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(regs)->bp = caller_frame_pointer(); \
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(regs)->cs = __KERNEL_CS; \
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regs->flags = 0; \
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asm volatile( \
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_ASM_MOV "%%"_ASM_SP ", %0\n" \
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: "=m" ((regs)->sp) \
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:: "memory" \
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); \
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}
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struct perf_guest_switch_msr {
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unsigned msr;
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u64 host, guest;
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};
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extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
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extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
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extern void perf_check_microcode(void);
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#else
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static inline struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
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{
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*nr = 0;
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return NULL;
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}
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static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
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{
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memset(cap, 0, sizeof(*cap));
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}
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static inline void perf_events_lapic_init(void) { }
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static inline void perf_check_microcode(void) { }
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#endif
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#ifdef CONFIG_CPU_SUP_INTEL
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extern void intel_pt_handle_vmx(int on);
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#endif
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#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
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extern void amd_pmu_enable_virt(void);
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extern void amd_pmu_disable_virt(void);
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#else
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static inline void amd_pmu_enable_virt(void) { }
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static inline void amd_pmu_disable_virt(void) { }
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#endif
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#define arch_perf_out_copy_user copy_from_user_nmi
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#endif /* _ASM_X86_PERF_EVENT_H */
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