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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b99bfca56e
This adds platform-specific declarations for the PSC clocks on TI DM355 based systems. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
89 lines
3.7 KiB
C
89 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PSC clock descriptions for TI DaVinci DM355
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*
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* Copyright (C) 2018 David Lechner <david@lechnology.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include "psc.h"
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LPSC_CLKDEV1(vpss_master_clkdev, "master", "vpss");
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LPSC_CLKDEV1(vpss_slave_clkdev, "slave", "vpss");
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LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1");
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LPSC_CLKDEV1(mmcsd1_clkdev, NULL, "dm6441-mmc.1");
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LPSC_CLKDEV1(mcbsp1_clkdev, NULL, "davinci-mcbsp.1");
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LPSC_CLKDEV1(usb_clkdev, "usb", NULL);
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LPSC_CLKDEV1(spi2_clkdev, NULL, "spi_davinci.2");
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LPSC_CLKDEV1(aemif_clkdev, "aemif", NULL);
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LPSC_CLKDEV1(mmcsd0_clkdev, NULL, "dm6441-mmc.0");
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LPSC_CLKDEV1(mcbsp0_clkdev, NULL, "davinci-mcbsp.0");
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LPSC_CLKDEV1(i2c_clkdev, NULL, "i2c_davinci.1");
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LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0");
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LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1");
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LPSC_CLKDEV1(uart2_clkdev, NULL, "serial8250.2");
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LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0");
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/* REVISIT: gpio-davinci.c should be modified to drop con_id */
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LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL);
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LPSC_CLKDEV1(timer0_clkdev, "timer0", NULL);
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LPSC_CLKDEV1(timer2_clkdev, NULL, "davinci-wdt");
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LPSC_CLKDEV1(vpss_dac_clkdev, "vpss_dac", NULL);
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static const struct davinci_lpsc_clk_info dm355_psc_info[] = {
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LPSC(0, 0, vpss_master, pll1_sysclk4, vpss_master_clkdev, 0),
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LPSC(1, 0, vpss_slave, pll1_sysclk4, vpss_slave_clkdev, 0),
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LPSC(5, 0, timer3, pll1_auxclk, NULL, 0),
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LPSC(6, 0, spi1, pll1_sysclk2, spi1_clkdev, 0),
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LPSC(7, 0, mmcsd1, pll1_sysclk2, mmcsd1_clkdev, 0),
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LPSC(8, 0, asp1, pll1_sysclk2, NULL, 0),
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LPSC(9, 0, usb, pll1_sysclk2, usb_clkdev, 0),
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LPSC(10, 0, pwm3, pll1_auxclk, NULL, 0),
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LPSC(11, 0, spi2, pll1_sysclk2, spi2_clkdev, 0),
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LPSC(12, 0, rto, pll1_auxclk, NULL, 0),
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LPSC(14, 0, aemif, pll1_sysclk2, aemif_clkdev, 0),
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LPSC(15, 0, mmcsd0, pll1_sysclk2, mmcsd0_clkdev, 0),
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LPSC(17, 0, asp0, pll1_sysclk2, NULL, 0),
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LPSC(18, 0, i2c, pll1_auxclk, i2c_clkdev, 0),
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LPSC(19, 0, uart0, pll1_auxclk, uart0_clkdev, 0),
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LPSC(20, 0, uart1, pll1_auxclk, uart1_clkdev, 0),
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LPSC(21, 0, uart2, pll1_sysclk2, uart2_clkdev, 0),
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LPSC(22, 0, spi0, pll1_sysclk2, spi0_clkdev, 0),
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LPSC(23, 0, pwm0, pll1_auxclk, NULL, 0),
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LPSC(24, 0, pwm1, pll1_auxclk, NULL, 0),
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LPSC(25, 0, pwm2, pll1_auxclk, NULL, 0),
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LPSC(26, 0, gpio, pll1_sysclk2, gpio_clkdev, 0),
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LPSC(27, 0, timer0, pll1_auxclk, timer0_clkdev, LPSC_ALWAYS_ENABLED),
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LPSC(28, 0, timer1, pll1_auxclk, NULL, 0),
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/* REVISIT: why can't this be disabled? */
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LPSC(29, 0, timer2, pll1_auxclk, timer2_clkdev, LPSC_ALWAYS_ENABLED),
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LPSC(31, 0, arm, pll1_sysclk1, NULL, LPSC_ALWAYS_ENABLED),
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LPSC(40, 0, mjcp, pll1_sysclk1, NULL, 0),
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LPSC(41, 0, vpss_dac, pll1_sysclk3, vpss_dac_clkdev, 0),
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{ }
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};
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static int dm355_psc_init(struct device *dev, void __iomem *base)
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{
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return davinci_psc_register_clocks(dev, dm355_psc_info, 42, base);
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}
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static struct clk_bulk_data dm355_psc_parent_clks[] = {
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{ .id = "pll1_sysclk1" },
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{ .id = "pll1_sysclk2" },
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{ .id = "pll1_sysclk3" },
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{ .id = "pll1_sysclk4" },
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{ .id = "pll1_auxclk" },
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};
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const struct davinci_psc_init_data dm355_psc_init_data = {
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.parent_clks = dm355_psc_parent_clks,
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.num_parent_clks = ARRAY_SIZE(dm355_psc_parent_clks),
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.psc_init = &dm355_psc_init,
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};
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