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fe6af0e122
Field FL/TPL in register TDES3 is not correctly set on GMAC4. TX appears to be functional on GMAC 4.10a even if this field is not set, however, to avoid relying on undefined behavior, set the length in TDES3. The field has a different meaning depending on if the TSE bit in TDES3 is set or not (TSO). However, regardless of the TSE bit, the field is not optional. The field is already set correctly when the TSE bit is set. Since there is no limit for the number of descriptors that can be used for a single packet, the field should be set to the sum of the buffers contained in: [<desc with First Descriptor bit set> ... <desc n> ... <desc with Last Descriptor bit set>], which should be equal to skb->len. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
180 lines
5.3 KiB
C
180 lines
5.3 KiB
C
/*******************************************************************************
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Specialised functions for managing Chained mode
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Copyright(C) 2011 STMicroelectronics Ltd
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It defines all the functions used to handle the normal/enhanced
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descriptors in case of the DMA is configured to work in chained or
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in ring mode.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include "stmmac.h"
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static int stmmac_jumbo_frm(void *p, struct sk_buff *skb, int csum)
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{
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struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)p;
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unsigned int nopaged_len = skb_headlen(skb);
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struct stmmac_priv *priv = tx_q->priv_data;
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unsigned int entry = tx_q->cur_tx;
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unsigned int bmax, des2;
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unsigned int i = 1, len;
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struct dma_desc *desc;
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desc = tx_q->dma_tx + entry;
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if (priv->plat->enh_desc)
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bmax = BUF_SIZE_8KiB;
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else
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bmax = BUF_SIZE_2KiB;
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len = nopaged_len - bmax;
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des2 = dma_map_single(priv->device, skb->data,
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bmax, DMA_TO_DEVICE);
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desc->des2 = cpu_to_le32(des2);
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if (dma_mapping_error(priv->device, des2))
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return -1;
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tx_q->tx_skbuff_dma[entry].buf = des2;
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tx_q->tx_skbuff_dma[entry].len = bmax;
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/* do not close the descriptor and do not set own bit */
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priv->hw->desc->prepare_tx_desc(desc, 1, bmax, csum, STMMAC_CHAIN_MODE,
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0, false, skb->len);
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while (len != 0) {
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tx_q->tx_skbuff[entry] = NULL;
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entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
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desc = tx_q->dma_tx + entry;
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if (len > bmax) {
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des2 = dma_map_single(priv->device,
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(skb->data + bmax * i),
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bmax, DMA_TO_DEVICE);
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desc->des2 = cpu_to_le32(des2);
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if (dma_mapping_error(priv->device, des2))
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return -1;
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tx_q->tx_skbuff_dma[entry].buf = des2;
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tx_q->tx_skbuff_dma[entry].len = bmax;
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priv->hw->desc->prepare_tx_desc(desc, 0, bmax, csum,
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STMMAC_CHAIN_MODE, 1,
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false, skb->len);
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len -= bmax;
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i++;
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} else {
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des2 = dma_map_single(priv->device,
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(skb->data + bmax * i), len,
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DMA_TO_DEVICE);
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desc->des2 = cpu_to_le32(des2);
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if (dma_mapping_error(priv->device, des2))
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return -1;
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tx_q->tx_skbuff_dma[entry].buf = des2;
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tx_q->tx_skbuff_dma[entry].len = len;
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/* last descriptor can be set now */
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priv->hw->desc->prepare_tx_desc(desc, 0, len, csum,
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STMMAC_CHAIN_MODE, 1,
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true, skb->len);
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len = 0;
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}
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}
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tx_q->cur_tx = entry;
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return entry;
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}
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static unsigned int stmmac_is_jumbo_frm(int len, int enh_desc)
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{
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unsigned int ret = 0;
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if ((enh_desc && (len > BUF_SIZE_8KiB)) ||
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(!enh_desc && (len > BUF_SIZE_2KiB))) {
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ret = 1;
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}
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return ret;
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}
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static void stmmac_init_dma_chain(void *des, dma_addr_t phy_addr,
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unsigned int size, unsigned int extend_desc)
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{
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/*
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* In chained mode the des3 points to the next element in the ring.
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* The latest element has to point to the head.
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*/
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int i;
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dma_addr_t dma_phy = phy_addr;
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if (extend_desc) {
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struct dma_extended_desc *p = (struct dma_extended_desc *)des;
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for (i = 0; i < (size - 1); i++) {
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dma_phy += sizeof(struct dma_extended_desc);
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p->basic.des3 = cpu_to_le32((unsigned int)dma_phy);
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p++;
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}
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p->basic.des3 = cpu_to_le32((unsigned int)phy_addr);
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} else {
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struct dma_desc *p = (struct dma_desc *)des;
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for (i = 0; i < (size - 1); i++) {
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dma_phy += sizeof(struct dma_desc);
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p->des3 = cpu_to_le32((unsigned int)dma_phy);
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p++;
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}
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p->des3 = cpu_to_le32((unsigned int)phy_addr);
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}
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}
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static void stmmac_refill_desc3(void *priv_ptr, struct dma_desc *p)
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{
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struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)priv_ptr;
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struct stmmac_priv *priv = rx_q->priv_data;
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if (priv->hwts_rx_en && !priv->extend_desc)
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/* NOTE: Device will overwrite des3 with timestamp value if
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* 1588-2002 time stamping is enabled, hence reinitialize it
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* to keep explicit chaining in the descriptor.
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*/
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p->des3 = cpu_to_le32((unsigned int)(rx_q->dma_rx_phy +
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(((rx_q->dirty_rx) + 1) %
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DMA_RX_SIZE) *
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sizeof(struct dma_desc)));
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}
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static void stmmac_clean_desc3(void *priv_ptr, struct dma_desc *p)
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{
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struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)priv_ptr;
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struct stmmac_priv *priv = tx_q->priv_data;
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unsigned int entry = tx_q->dirty_tx;
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if (tx_q->tx_skbuff_dma[entry].last_segment && !priv->extend_desc &&
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priv->hwts_tx_en)
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/* NOTE: Device will overwrite des3 with timestamp value if
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* 1588-2002 time stamping is enabled, hence reinitialize it
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* to keep explicit chaining in the descriptor.
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*/
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p->des3 = cpu_to_le32((unsigned int)((tx_q->dma_tx_phy +
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((tx_q->dirty_tx + 1) % DMA_TX_SIZE))
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* sizeof(struct dma_desc)));
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}
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const struct stmmac_mode_ops chain_mode_ops = {
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.init = stmmac_init_dma_chain,
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.is_jumbo_frm = stmmac_is_jumbo_frm,
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.jumbo_frm = stmmac_jumbo_frm,
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.refill_desc3 = stmmac_refill_desc3,
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.clean_desc3 = stmmac_clean_desc3,
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};
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