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The A83T SoC has a camera sensor interface (known as CSI in Allwinner lingo), which is similar to the one found on the A64 and H3. The only difference seems to be that support of MIPI CSI through a connected MIPI CSI-2 bridge. Add a compatible string for this variant. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
62 lines
1.9 KiB
Plaintext
62 lines
1.9 KiB
Plaintext
Allwinner V3s Camera Sensor Interface
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-------------------------------------
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Allwinner V3s SoC features a CSI module(CSI1) with parallel interface.
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Required properties:
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- compatible: value must be one of:
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* "allwinner,sun6i-a31-csi"
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* "allwinner,sun8i-a83t-csi"
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* "allwinner,sun8i-h3-csi"
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* "allwinner,sun8i-v3s-csi"
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* "allwinner,sun50i-a64-csi"
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- reg: base address and size of the memory-mapped region.
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- interrupts: interrupt associated to this IP
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- clocks: phandles to the clocks feeding the CSI
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* bus: the CSI interface clock
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* mod: the CSI module clock
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* ram: the CSI DRAM clock
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- clock-names: the clock names mentioned above
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- resets: phandles to the reset line driving the CSI
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The CSI node should contain one 'port' child node with one child 'endpoint'
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node, according to the bindings defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt.
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Endpoint node properties for CSI
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---------------------------------
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See the video-interfaces.txt for a detailed description of these properties.
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- remote-endpoint : (required) a phandle to the bus receiver's endpoint
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node
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- bus-width: : (required) must be 8, 10, 12 or 16
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- pclk-sample : (optional) (default: sample on falling edge)
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- hsync-active : (required; parallel-only)
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- vsync-active : (required; parallel-only)
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Example:
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csi1: csi@1cb4000 {
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compatible = "allwinner,sun8i-v3s-csi";
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reg = <0x01cb4000 0x1000>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_CSI>,
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<&ccu CLK_CSI1_SCLK>,
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<&ccu CLK_DRAM_CSI>;
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clock-names = "bus", "mod", "ram";
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resets = <&ccu RST_BUS_CSI>;
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port {
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/* Parallel bus endpoint */
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csi1_ep: endpoint {
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remote-endpoint = <&adv7611_ep>;
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bus-width = <16>;
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/* If hsync-active/vsync-active are missing,
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embedded BT.656 sync is used */
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hsync-active = <0>; /* Active low */
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vsync-active = <0>; /* Active low */
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pclk-sample = <1>; /* Rising */
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};
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};
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};
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