mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
b58439916b
Add binding document for the Cadence QSPI controller. Signed-off-by: Graham Moore <grmoore@opensource.altera.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alan Tull <atull@opensource.altera.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Graham Moore <grmoore@opensource.altera.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Yves Vandervennet <yvanderv@opensource.altera.com> Cc: devicetree@vger.kernel.org Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
57 lines
1.9 KiB
Plaintext
57 lines
1.9 KiB
Plaintext
* Cadence Quad SPI controller
|
|
|
|
Required properties:
|
|
- compatible : Should be "cdns,qspi-nor".
|
|
- reg : Contains two entries, each of which is a tuple consisting of a
|
|
physical address and length. The first entry is the address and
|
|
length of the controller register set. The second entry is the
|
|
address and length of the QSPI Controller data area.
|
|
- interrupts : Unit interrupt specifier for the controller interrupt.
|
|
- clocks : phandle to the Quad SPI clock.
|
|
- cdns,fifo-depth : Size of the data FIFO in words.
|
|
- cdns,fifo-width : Bus width of the data FIFO in bytes.
|
|
- cdns,trigger-address : 32-bit indirect AHB trigger address.
|
|
|
|
Optional properties:
|
|
- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
|
|
|
|
Optional subnodes:
|
|
Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
|
|
custom properties:
|
|
- cdns,read-delay : Delay for read capture logic, in clock cycles
|
|
- cdns,tshsl-ns : Delay in nanoseconds for the length that the master
|
|
mode chip select outputs are de-asserted between
|
|
transactions.
|
|
- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being
|
|
de-activated and the activation of another.
|
|
- cdns,tchsh-ns : Delay in nanoseconds between last bit of current
|
|
transaction and deasserting the device chip select
|
|
(qspi_n_ss_out).
|
|
- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low
|
|
and first bit transfer.
|
|
|
|
Example:
|
|
|
|
qspi: spi@ff705000 {
|
|
compatible = "cdns,qspi-nor";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xff705000 0x1000>,
|
|
<0xffa00000 0x1000>;
|
|
interrupts = <0 151 4>;
|
|
clocks = <&qspi_clk>;
|
|
cdns,is-decoded-cs;
|
|
cdns,fifo-depth = <128>;
|
|
cdns,fifo-width = <4>;
|
|
cdns,trigger-address = <0x00000000>;
|
|
|
|
flash0: n25q00@0 {
|
|
...
|
|
cdns,read-delay = <4>;
|
|
cdns,tshsl-ns = <50>;
|
|
cdns,tsd2d-ns = <50>;
|
|
cdns,tchsh-ns = <4>;
|
|
cdns,tslch-ns = <4>;
|
|
};
|
|
};
|