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d27f9d634c
This adds a node describing the six external interrupt lines IRQ0-IRQ5 with configurable polarity. Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
1007 lines
27 KiB
Plaintext
1007 lines
27 KiB
Plaintext
/*
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* Copyright 2013-2014 Freescale Semiconductor, Inc.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this file; if not, write to the Free
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* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "fsl,ls1021a";
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interrupt-parent = <&gic>;
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aliases {
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crypto = &crypto;
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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serial0 = &lpuart0;
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serial1 = &lpuart1;
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serial2 = &lpuart2;
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serial3 = &lpuart3;
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serial4 = &lpuart4;
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serial5 = &lpuart5;
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sysclk = &sysclk;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@f00 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0xf00>;
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clocks = <&clockgen 1 0>;
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#cooling-cells = <2>;
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};
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cpu1: cpu@f01 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0xf01>;
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clocks = <&clockgen 1 0>;
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#cooling-cells = <2>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x0>;
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};
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sysclk: sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "sysclk";
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>;
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};
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reboot {
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compatible = "syscon-reboot";
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regmap = <&dcfg>;
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offset = <0xb0>;
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mask = <0x02>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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device_type = "soc";
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interrupt-parent = <&gic>;
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ranges;
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ddr: memory-controller@1080000 {
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compatible = "fsl,qoriq-memory-controller";
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reg = <0x0 0x1080000 0x0 0x1000>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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big-endian;
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};
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gic: interrupt-controller@1400000 {
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compatible = "arm,gic-400", "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x1401000 0x0 0x1000>,
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<0x0 0x1402000 0x0 0x2000>,
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<0x0 0x1404000 0x0 0x2000>,
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<0x0 0x1406000 0x0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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msi1: msi-controller@1570e00 {
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compatible = "fsl,ls1021a-msi";
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reg = <0x0 0x1570e00 0x0 0x8>;
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msi-controller;
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interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
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};
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msi2: msi-controller@1570e08 {
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compatible = "fsl,ls1021a-msi";
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reg = <0x0 0x1570e08 0x0 0x8>;
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msi-controller;
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interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
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};
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ifc: ifc@1530000 {
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compatible = "fsl,ifc", "simple-bus";
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reg = <0x0 0x1530000 0x0 0x10000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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};
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dcfg: dcfg@1ee0000 {
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compatible = "fsl,ls1021a-dcfg", "syscon";
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reg = <0x0 0x1ee0000 0x0 0x10000>;
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big-endian;
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};
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qspi: spi@1550000 {
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compatible = "fsl,ls1021a-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x1550000 0x0 0x10000>,
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<0x0 0x40000000 0x0 0x40000000>;
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reg-names = "QuadSPI", "QuadSPI-memory";
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interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "qspi_en", "qspi";
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clocks = <&clockgen 4 1>, <&clockgen 4 1>;
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status = "disabled";
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};
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esdhc: esdhc@1560000 {
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compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
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reg = <0x0 0x1560000 0x0 0x10000>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <0>;
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voltage-ranges = <1800 1800 3300 3300>;
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sdhci,auto-cmd12;
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big-endian;
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bus-width = <4>;
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status = "disabled";
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};
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sata: sata@3200000 {
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compatible = "fsl,ls1021a-ahci";
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reg = <0x0 0x3200000 0x0 0x10000>,
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<0x0 0x20220520 0x0 0x4>;
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reg-names = "ahci", "sata-ecc";
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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dma-coherent;
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status = "disabled";
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};
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scfg: scfg@1570000 {
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compatible = "fsl,ls1021a-scfg", "syscon";
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reg = <0x0 0x1570000 0x0 0x10000>;
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big-endian;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x1570000 0x10000>;
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extirq: interrupt-controller@1ac {
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compatible = "fsl,ls1021a-extirq";
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#interrupt-cells = <2>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x1ac 4>;
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interrupt-map =
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<0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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<1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
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<2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
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<3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
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<4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
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<5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-map-mask = <0xffffffff 0x0>;
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};
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};
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crypto: crypto@1700000 {
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compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
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fsl,sec-era = <7>;
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0 0x1700000 0x0 0x100000>;
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ranges = <0x0 0x0 0x1700000 0x100000>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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sec_jr0: jr@10000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x10000 0x10000>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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};
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sec_jr1: jr@20000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x20000 0x10000>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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};
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sec_jr2: jr@30000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x30000 0x10000>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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};
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sec_jr3: jr@40000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x40000 0x10000>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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clockgen: clocking@1ee1000 {
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compatible = "fsl,ls1021a-clockgen";
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reg = <0x0 0x1ee1000 0x0 0x1000>;
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#clock-cells = <2>;
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clocks = <&sysclk>;
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};
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tmu: tmu@1f00000 {
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compatible = "fsl,qoriq-tmu";
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reg = <0x0 0x1f00000 0x0 0x10000>;
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
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fsl,tmu-calibration = <0x00000000 0x0000000f
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0x00000001 0x00000017
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0x00000002 0x0000001e
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0x00000003 0x00000026
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0x00000004 0x0000002e
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0x00000005 0x00000035
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0x00000006 0x0000003d
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0x00000007 0x00000044
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0x00000008 0x0000004c
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0x00000009 0x00000053
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0x0000000a 0x0000005b
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0x0000000b 0x00000064
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0x00010000 0x00000011
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0x00010001 0x0000001c
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0x00010002 0x00000024
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0x00010003 0x0000002b
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0x00010004 0x00000034
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0x00010005 0x00000039
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0x00010006 0x00000042
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0x00010007 0x0000004c
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0x00010008 0x00000051
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0x00010009 0x0000005a
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0x0001000a 0x00000063
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0x00020000 0x00000013
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0x00020001 0x00000019
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0x00020002 0x00000024
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0x00020003 0x0000002c
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0x00020004 0x00000035
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0x00020005 0x0000003d
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0x00020006 0x00000046
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0x00020007 0x00000050
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0x00020008 0x00000059
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0x00030000 0x00000002
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0x00030001 0x0000000d
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0x00030002 0x00000019
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0x00030003 0x00000024>;
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#thermal-sensor-cells = <1>;
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};
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thermal-zones {
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cpu_thermal: cpu-thermal {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 0>;
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trips {
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cpu_alert: cpu-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu-crit {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT
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THERMAL_NO_LIMIT>,
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<&cpu1 THERMAL_NO_LIMIT
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THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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dspi0: spi@2100000 {
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compatible = "fsl,ls1021a-v1.0-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2100000 0x0 0x10000>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "dspi";
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clocks = <&clockgen 4 1>;
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spi-num-chipselects = <6>;
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big-endian;
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status = "disabled";
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};
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dspi1: spi@2110000 {
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compatible = "fsl,ls1021a-v1.0-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2110000 0x0 0x10000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "dspi";
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clocks = <&clockgen 4 1>;
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spi-num-chipselects = <6>;
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big-endian;
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status = "disabled";
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};
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i2c0: i2c@2180000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2180000 0x0 0x10000>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&clockgen 4 1>;
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dma-names = "tx", "rx";
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dmas = <&edma0 1 39>, <&edma0 1 38>;
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status = "disabled";
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};
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i2c1: i2c@2190000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2190000 0x0 0x10000>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&clockgen 4 1>;
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dma-names = "tx", "rx";
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dmas = <&edma0 1 37>, <&edma0 1 36>;
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status = "disabled";
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};
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i2c2: i2c@21a0000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x21a0000 0x0 0x10000>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&clockgen 4 1>;
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dma-names = "tx", "rx";
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dmas = <&edma0 1 35>, <&edma0 1 34>;
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status = "disabled";
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};
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uart0: serial@21c0500 {
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compatible = "fsl,16550-FIFO64", "ns16550a";
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reg = <0x0 0x21c0500 0x0 0x100>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <0>;
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fifo-size = <15>;
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status = "disabled";
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};
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uart1: serial@21c0600 {
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compatible = "fsl,16550-FIFO64", "ns16550a";
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reg = <0x0 0x21c0600 0x0 0x100>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <0>;
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fifo-size = <15>;
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status = "disabled";
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};
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uart2: serial@21d0500 {
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compatible = "fsl,16550-FIFO64", "ns16550a";
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reg = <0x0 0x21d0500 0x0 0x100>;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <0>;
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fifo-size = <15>;
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status = "disabled";
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};
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uart3: serial@21d0600 {
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compatible = "fsl,16550-FIFO64", "ns16550a";
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reg = <0x0 0x21d0600 0x0 0x100>;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <0>;
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fifo-size = <15>;
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status = "disabled";
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};
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counter0: counter@29d0000 {
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compatible = "fsl,ftm-quaddec";
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reg = <0x0 0x29d0000 0x0 0x10000>;
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big-endian;
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status = "disabled";
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};
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counter1: counter@29e0000 {
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compatible = "fsl,ftm-quaddec";
|
|
reg = <0x0 0x29e0000 0x0 0x10000>;
|
|
big-endian;
|
|
status = "disabled";
|
|
};
|
|
|
|
counter2: counter@29f0000 {
|
|
compatible = "fsl,ftm-quaddec";
|
|
reg = <0x0 0x29f0000 0x0 0x10000>;
|
|
big-endian;
|
|
status = "disabled";
|
|
};
|
|
|
|
counter3: counter@2a00000 {
|
|
compatible = "fsl,ftm-quaddec";
|
|
reg = <0x0 0x2a00000 0x0 0x10000>;
|
|
big-endian;
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio0: gpio@2300000 {
|
|
compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
|
|
reg = <0x0 0x2300000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio1: gpio@2310000 {
|
|
compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
|
|
reg = <0x0 0x2310000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio@2320000 {
|
|
compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
|
|
reg = <0x0 0x2320000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio@2330000 {
|
|
compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
|
|
reg = <0x0 0x2330000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
lpuart0: serial@2950000 {
|
|
compatible = "fsl,ls1021a-lpuart";
|
|
reg = <0x0 0x2950000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&sysclk>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart1: serial@2960000 {
|
|
compatible = "fsl,ls1021a-lpuart";
|
|
reg = <0x0 0x2960000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 1>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart2: serial@2970000 {
|
|
compatible = "fsl,ls1021a-lpuart";
|
|
reg = <0x0 0x2970000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 1>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart3: serial@2980000 {
|
|
compatible = "fsl,ls1021a-lpuart";
|
|
reg = <0x0 0x2980000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 1>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart4: serial@2990000 {
|
|
compatible = "fsl,ls1021a-lpuart";
|
|
reg = <0x0 0x2990000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 1>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart5: serial@29a0000 {
|
|
compatible = "fsl,ls1021a-lpuart";
|
|
reg = <0x0 0x29a0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 1>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm0: pwm@29d0000 {
|
|
compatible = "fsl,vf610-ftm-pwm";
|
|
#pwm-cells = <3>;
|
|
reg = <0x0 0x29d0000 0x0 0x10000>;
|
|
clock-names = "ftm_sys", "ftm_ext",
|
|
"ftm_fix", "ftm_cnt_clk_en";
|
|
clocks = <&clockgen 4 1>, <&clockgen 4 1>,
|
|
<&clockgen 4 1>, <&clockgen 4 1>;
|
|
big-endian;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@29e0000 {
|
|
compatible = "fsl,vf610-ftm-pwm";
|
|
#pwm-cells = <3>;
|
|
reg = <0x0 0x29e0000 0x0 0x10000>;
|
|
clock-names = "ftm_sys", "ftm_ext",
|
|
"ftm_fix", "ftm_cnt_clk_en";
|
|
clocks = <&clockgen 4 1>, <&clockgen 4 1>,
|
|
<&clockgen 4 1>, <&clockgen 4 1>;
|
|
big-endian;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@29f0000 {
|
|
compatible = "fsl,vf610-ftm-pwm";
|
|
#pwm-cells = <3>;
|
|
reg = <0x0 0x29f0000 0x0 0x10000>;
|
|
clock-names = "ftm_sys", "ftm_ext",
|
|
"ftm_fix", "ftm_cnt_clk_en";
|
|
clocks = <&clockgen 4 1>, <&clockgen 4 1>,
|
|
<&clockgen 4 1>, <&clockgen 4 1>;
|
|
big-endian;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@2a00000 {
|
|
compatible = "fsl,vf610-ftm-pwm";
|
|
#pwm-cells = <3>;
|
|
reg = <0x0 0x2a00000 0x0 0x10000>;
|
|
clock-names = "ftm_sys", "ftm_ext",
|
|
"ftm_fix", "ftm_cnt_clk_en";
|
|
clocks = <&clockgen 4 1>, <&clockgen 4 1>,
|
|
<&clockgen 4 1>, <&clockgen 4 1>;
|
|
big-endian;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm4: pwm@2a10000 {
|
|
compatible = "fsl,vf610-ftm-pwm";
|
|
#pwm-cells = <3>;
|
|
reg = <0x0 0x2a10000 0x0 0x10000>;
|
|
clock-names = "ftm_sys", "ftm_ext",
|
|
"ftm_fix", "ftm_cnt_clk_en";
|
|
clocks = <&clockgen 4 1>, <&clockgen 4 1>,
|
|
<&clockgen 4 1>, <&clockgen 4 1>;
|
|
big-endian;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm5: pwm@2a20000 {
|
|
compatible = "fsl,vf610-ftm-pwm";
|
|
#pwm-cells = <3>;
|
|
reg = <0x0 0x2a20000 0x0 0x10000>;
|
|
clock-names = "ftm_sys", "ftm_ext",
|
|
"ftm_fix", "ftm_cnt_clk_en";
|
|
clocks = <&clockgen 4 1>, <&clockgen 4 1>,
|
|
<&clockgen 4 1>, <&clockgen 4 1>;
|
|
big-endian;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm6: pwm@2a30000 {
|
|
compatible = "fsl,vf610-ftm-pwm";
|
|
#pwm-cells = <3>;
|
|
reg = <0x0 0x2a30000 0x0 0x10000>;
|
|
clock-names = "ftm_sys", "ftm_ext",
|
|
"ftm_fix", "ftm_cnt_clk_en";
|
|
clocks = <&clockgen 4 1>, <&clockgen 4 1>,
|
|
<&clockgen 4 1>, <&clockgen 4 1>;
|
|
big-endian;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm7: pwm@2a40000 {
|
|
compatible = "fsl,vf610-ftm-pwm";
|
|
#pwm-cells = <3>;
|
|
reg = <0x0 0x2a40000 0x0 0x10000>;
|
|
clock-names = "ftm_sys", "ftm_ext",
|
|
"ftm_fix", "ftm_cnt_clk_en";
|
|
clocks = <&clockgen 4 1>, <&clockgen 4 1>,
|
|
<&clockgen 4 1>, <&clockgen 4 1>;
|
|
big-endian;
|
|
status = "disabled";
|
|
};
|
|
|
|
wdog0: watchdog@2ad0000 {
|
|
compatible = "fsl,imx21-wdt";
|
|
reg = <0x0 0x2ad0000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 1>;
|
|
clock-names = "wdog-en";
|
|
big-endian;
|
|
};
|
|
|
|
sai1: sai@2b50000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "fsl,vf610-sai";
|
|
reg = <0x0 0x2b50000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 1>, <&clockgen 4 1>,
|
|
<&clockgen 4 1>, <&clockgen 4 1>;
|
|
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
|
dma-names = "tx", "rx";
|
|
dmas = <&edma0 1 47>,
|
|
<&edma0 1 46>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sai2: sai@2b60000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "fsl,vf610-sai";
|
|
reg = <0x0 0x2b60000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 1>, <&clockgen 4 1>,
|
|
<&clockgen 4 1>, <&clockgen 4 1>;
|
|
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
|
dma-names = "tx", "rx";
|
|
dmas = <&edma0 1 45>,
|
|
<&edma0 1 44>;
|
|
status = "disabled";
|
|
};
|
|
|
|
edma0: edma@2c00000 {
|
|
#dma-cells = <2>;
|
|
compatible = "fsl,vf610-edma";
|
|
reg = <0x0 0x2c00000 0x0 0x10000>,
|
|
<0x0 0x2c10000 0x0 0x10000>,
|
|
<0x0 0x2c20000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "edma-tx", "edma-err";
|
|
dma-channels = <32>;
|
|
big-endian;
|
|
clock-names = "dmamux0", "dmamux1";
|
|
clocks = <&clockgen 4 1>,
|
|
<&clockgen 4 1>;
|
|
};
|
|
|
|
dcu: dcu@2ce0000 {
|
|
compatible = "fsl,ls1021a-dcu";
|
|
reg = <0x0 0x2ce0000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 0>,
|
|
<&clockgen 4 0>;
|
|
clock-names = "dcu", "pix";
|
|
big-endian;
|
|
status = "disabled";
|
|
};
|
|
|
|
mdio0: mdio@2d24000 {
|
|
compatible = "fsl,etsec2-mdio";
|
|
device_type = "mdio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x2d24000 0x0 0x4000>,
|
|
<0x0 0x2d10030 0x0 0x4>;
|
|
};
|
|
|
|
mdio1: mdio@2d64000 {
|
|
compatible = "fsl,etsec2-mdio";
|
|
device_type = "mdio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x2d64000 0x0 0x4000>,
|
|
<0x0 0x2d50030 0x0 0x4>;
|
|
};
|
|
|
|
ptp_clock@2d10e00 {
|
|
compatible = "fsl,etsec-ptp";
|
|
reg = <0x0 0x2d10e00 0x0 0xb0>;
|
|
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
|
fsl,tclk-period = <5>;
|
|
fsl,tmr-prsc = <2>;
|
|
fsl,tmr-add = <0xaaaaaaab>;
|
|
fsl,tmr-fiper1 = <999999995>;
|
|
fsl,tmr-fiper2 = <99990>;
|
|
fsl,max-adj = <499999999>;
|
|
fsl,extts-fifo;
|
|
};
|
|
|
|
enet0: ethernet@2d10000 {
|
|
compatible = "fsl,etsec2";
|
|
device_type = "network";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
interrupt-parent = <&gic>;
|
|
model = "eTSEC";
|
|
fsl,magic-packet;
|
|
ranges;
|
|
dma-coherent;
|
|
|
|
queue-group@2d10000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
reg = <0x0 0x2d10000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
queue-group@2d14000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
reg = <0x0 0x2d14000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
enet1: ethernet@2d50000 {
|
|
compatible = "fsl,etsec2";
|
|
device_type = "network";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
interrupt-parent = <&gic>;
|
|
model = "eTSEC";
|
|
ranges;
|
|
dma-coherent;
|
|
|
|
queue-group@2d50000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
reg = <0x0 0x2d50000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
queue-group@2d54000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
reg = <0x0 0x2d54000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
enet2: ethernet@2d90000 {
|
|
compatible = "fsl,etsec2";
|
|
device_type = "network";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
interrupt-parent = <&gic>;
|
|
model = "eTSEC";
|
|
ranges;
|
|
dma-coherent;
|
|
|
|
queue-group@2d90000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
reg = <0x0 0x2d90000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
queue-group@2d94000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
reg = <0x0 0x2d94000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
usb2: usb@8600000 {
|
|
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
|
|
reg = <0x0 0x8600000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
|
|
dr_mode = "host";
|
|
phy_type = "ulpi";
|
|
};
|
|
|
|
usb3: usb3@3100000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x0 0x3100000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
dr_mode = "host";
|
|
snps,quirk-frame-length-adjustment = <0x20>;
|
|
snps,dis_rxdet_inp3_quirk;
|
|
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
|
};
|
|
|
|
pcie@3400000 {
|
|
compatible = "fsl,ls1021a-pcie";
|
|
reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
|
|
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
reg-names = "regs", "config";
|
|
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
|
fsl,pcie-scfg = <&scfg 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
num-viewport = <6>;
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
msi-parent = <&msi1>, <&msi2>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie@3500000 {
|
|
compatible = "fsl,ls1021a-pcie";
|
|
reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
|
|
0x48 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
reg-names = "regs", "config";
|
|
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
|
|
fsl,pcie-scfg = <&scfg 1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
num-viewport = <6>;
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
msi-parent = <&msi1>, <&msi2>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
can0: can@2a70000 {
|
|
compatible = "fsl,ls1021ar2-flexcan";
|
|
reg = <0x0 0x2a70000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 1>, <&clockgen 4 1>;
|
|
clock-names = "ipg", "per";
|
|
big-endian;
|
|
};
|
|
|
|
can1: can@2a80000 {
|
|
compatible = "fsl,ls1021ar2-flexcan";
|
|
reg = <0x0 0x2a80000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 1>, <&clockgen 4 1>;
|
|
clock-names = "ipg", "per";
|
|
big-endian;
|
|
};
|
|
|
|
can2: can@2a90000 {
|
|
compatible = "fsl,ls1021ar2-flexcan";
|
|
reg = <0x0 0x2a90000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 1>, <&clockgen 4 1>;
|
|
clock-names = "ipg", "per";
|
|
big-endian;
|
|
};
|
|
|
|
can3: can@2aa0000 {
|
|
compatible = "fsl,ls1021ar2-flexcan";
|
|
reg = <0x0 0x2aa0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 1>, <&clockgen 4 1>;
|
|
clock-names = "ipg", "per";
|
|
big-endian;
|
|
};
|
|
|
|
ocram1: sram@10000000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0x0 0x10000000 0x0 0x10000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x0 0x10000000 0x10000>;
|
|
};
|
|
|
|
ocram2: sram@10010000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0x0 0x10010000 0x0 0x10000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x0 0x10010000 0x10000>;
|
|
};
|
|
|
|
qdma: dma-controller@8390000 {
|
|
compatible = "fsl,ls1021a-qdma";
|
|
reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
|
|
<0x0 0x8389000 0x0 0x1000>, /* Status regs */
|
|
<0x0 0x838a000 0x0 0x2000>; /* Block regs */
|
|
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "qdma-error",
|
|
"qdma-queue0", "qdma-queue1";
|
|
dma-channels = <8>;
|
|
block-number = <1>;
|
|
block-offset = <0x1000>;
|
|
fsl,dma-queues = <2>;
|
|
status-sizes = <64>;
|
|
queue-sizes = <64 64>;
|
|
big-endian;
|
|
};
|
|
|
|
};
|
|
};
|