mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-17 11:16:48 +07:00
697 lines
17 KiB
C
697 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright © 2015 Intel Corporation.
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*
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* Authors: David Woodhouse <dwmw2@infradead.org>
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*/
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#include <linux/intel-iommu.h>
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#include <linux/mmu_notifier.h>
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#include <linux/sched.h>
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#include <linux/sched/mm.h>
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#include <linux/slab.h>
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#include <linux/intel-svm.h>
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#include <linux/rculist.h>
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#include <linux/pci.h>
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#include <linux/pci-ats.h>
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#include <linux/dmar.h>
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#include <linux/interrupt.h>
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#include <linux/mm_types.h>
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#include <linux/ioasid.h>
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#include <asm/page.h>
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#include "intel-pasid.h"
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static irqreturn_t prq_event_thread(int irq, void *d);
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#define PRQ_ORDER 0
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int intel_svm_enable_prq(struct intel_iommu *iommu)
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{
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struct page *pages;
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int irq, ret;
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pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
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if (!pages) {
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pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
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iommu->name);
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return -ENOMEM;
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}
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iommu->prq = page_address(pages);
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irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
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if (irq <= 0) {
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pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
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iommu->name);
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ret = -EINVAL;
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err:
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free_pages((unsigned long)iommu->prq, PRQ_ORDER);
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iommu->prq = NULL;
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return ret;
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}
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iommu->pr_irq = irq;
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snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
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ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
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iommu->prq_name, iommu);
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if (ret) {
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pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
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iommu->name);
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dmar_free_hwirq(irq);
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iommu->pr_irq = 0;
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goto err;
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}
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dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
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dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
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dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
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return 0;
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}
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int intel_svm_finish_prq(struct intel_iommu *iommu)
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{
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dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
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dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
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dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
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if (iommu->pr_irq) {
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free_irq(iommu->pr_irq, iommu);
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dmar_free_hwirq(iommu->pr_irq);
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iommu->pr_irq = 0;
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}
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free_pages((unsigned long)iommu->prq, PRQ_ORDER);
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iommu->prq = NULL;
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return 0;
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}
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static inline bool intel_svm_capable(struct intel_iommu *iommu)
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{
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return iommu->flags & VTD_FLAG_SVM_CAPABLE;
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}
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void intel_svm_check(struct intel_iommu *iommu)
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{
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if (!pasid_supported(iommu))
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return;
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if (cpu_feature_enabled(X86_FEATURE_GBPAGES) &&
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!cap_fl1gp_support(iommu->cap)) {
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pr_err("%s SVM disabled, incompatible 1GB page capability\n",
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iommu->name);
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return;
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}
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if (cpu_feature_enabled(X86_FEATURE_LA57) &&
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!cap_5lp_support(iommu->cap)) {
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pr_err("%s SVM disabled, incompatible paging mode\n",
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iommu->name);
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return;
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}
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iommu->flags |= VTD_FLAG_SVM_CAPABLE;
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}
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static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
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unsigned long address, unsigned long pages, int ih)
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{
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struct qi_desc desc;
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if (pages == -1) {
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desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
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QI_EIOTLB_DID(sdev->did) |
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QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
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QI_EIOTLB_TYPE;
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desc.qw1 = 0;
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} else {
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int mask = ilog2(__roundup_pow_of_two(pages));
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desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
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QI_EIOTLB_DID(sdev->did) |
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QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) |
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QI_EIOTLB_TYPE;
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desc.qw1 = QI_EIOTLB_ADDR(address) |
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QI_EIOTLB_IH(ih) |
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QI_EIOTLB_AM(mask);
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}
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desc.qw2 = 0;
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desc.qw3 = 0;
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qi_submit_sync(&desc, svm->iommu);
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if (sdev->dev_iotlb) {
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desc.qw0 = QI_DEV_EIOTLB_PASID(svm->pasid) |
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QI_DEV_EIOTLB_SID(sdev->sid) |
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QI_DEV_EIOTLB_QDEP(sdev->qdep) |
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QI_DEIOTLB_TYPE;
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if (pages == -1) {
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desc.qw1 = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) |
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QI_DEV_EIOTLB_SIZE;
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} else if (pages > 1) {
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/* The least significant zero bit indicates the size. So,
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* for example, an "address" value of 0x12345f000 will
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* flush from 0x123440000 to 0x12347ffff (256KiB). */
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unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT);
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unsigned long mask = __rounddown_pow_of_two(address ^ last);
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desc.qw1 = QI_DEV_EIOTLB_ADDR((address & ~mask) |
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(mask - 1)) | QI_DEV_EIOTLB_SIZE;
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} else {
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desc.qw1 = QI_DEV_EIOTLB_ADDR(address);
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}
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desc.qw2 = 0;
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desc.qw3 = 0;
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qi_submit_sync(&desc, svm->iommu);
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}
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}
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static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
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unsigned long pages, int ih)
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{
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struct intel_svm_dev *sdev;
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rcu_read_lock();
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list_for_each_entry_rcu(sdev, &svm->devs, list)
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intel_flush_svm_range_dev(svm, sdev, address, pages, ih);
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rcu_read_unlock();
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}
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/* Pages have been freed at this point */
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static void intel_invalidate_range(struct mmu_notifier *mn,
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struct mm_struct *mm,
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unsigned long start, unsigned long end)
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{
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struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
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intel_flush_svm_range(svm, start,
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(end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0);
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}
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static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
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{
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struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
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struct intel_svm_dev *sdev;
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/* This might end up being called from exit_mmap(), *before* the page
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* tables are cleared. And __mmu_notifier_release() will delete us from
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* the list of notifiers so that our invalidate_range() callback doesn't
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* get called when the page tables are cleared. So we need to protect
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* against hardware accessing those page tables.
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*
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* We do it by clearing the entry in the PASID table and then flushing
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* the IOTLB and the PASID table caches. This might upset hardware;
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* perhaps we'll want to point the PASID to a dummy PGD (like the zero
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* page) so that we end up taking a fault that the hardware really
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* *has* to handle gracefully without affecting other processes.
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*/
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rcu_read_lock();
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list_for_each_entry_rcu(sdev, &svm->devs, list) {
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intel_pasid_tear_down_entry(svm->iommu, sdev->dev, svm->pasid);
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intel_flush_svm_range_dev(svm, sdev, 0, -1, 0);
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}
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rcu_read_unlock();
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}
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static const struct mmu_notifier_ops intel_mmuops = {
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.release = intel_mm_release,
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.invalidate_range = intel_invalidate_range,
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};
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static DEFINE_MUTEX(pasid_mutex);
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static LIST_HEAD(global_svm_list);
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#define for_each_svm_dev(sdev, svm, d) \
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list_for_each_entry((sdev), &(svm)->devs, list) \
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if ((d) != (sdev)->dev) {} else
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int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops)
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{
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struct intel_iommu *iommu = intel_svm_device_to_iommu(dev);
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struct device_domain_info *info;
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struct intel_svm_dev *sdev;
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struct intel_svm *svm = NULL;
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struct mm_struct *mm = NULL;
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int pasid_max;
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int ret;
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if (!iommu || dmar_disabled)
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return -EINVAL;
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if (!intel_svm_capable(iommu))
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return -ENOTSUPP;
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if (dev_is_pci(dev)) {
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pasid_max = pci_max_pasids(to_pci_dev(dev));
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if (pasid_max < 0)
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return -EINVAL;
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} else
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pasid_max = 1 << 20;
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if (flags & SVM_FLAG_SUPERVISOR_MODE) {
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if (!ecap_srs(iommu->ecap))
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return -EINVAL;
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} else if (pasid) {
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mm = get_task_mm(current);
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BUG_ON(!mm);
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}
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mutex_lock(&pasid_mutex);
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if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) {
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struct intel_svm *t;
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list_for_each_entry(t, &global_svm_list, list) {
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if (t->mm != mm || (t->flags & SVM_FLAG_PRIVATE_PASID))
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continue;
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svm = t;
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if (svm->pasid >= pasid_max) {
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dev_warn(dev,
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"Limited PASID width. Cannot use existing PASID %d\n",
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svm->pasid);
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ret = -ENOSPC;
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goto out;
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}
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/* Find the matching device in svm list */
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for_each_svm_dev(sdev, svm, dev) {
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if (sdev->ops != ops) {
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ret = -EBUSY;
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goto out;
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}
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sdev->users++;
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goto success;
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}
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break;
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}
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}
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sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
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if (!sdev) {
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ret = -ENOMEM;
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goto out;
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}
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sdev->dev = dev;
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ret = intel_iommu_enable_pasid(iommu, dev);
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if (ret || !pasid) {
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/* If they don't actually want to assign a PASID, this is
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* just an enabling check/preparation. */
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kfree(sdev);
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goto out;
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}
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info = dev->archdata.iommu;
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if (!info || !info->pasid_supported) {
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kfree(sdev);
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goto out;
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}
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sdev->did = FLPT_DEFAULT_DID;
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sdev->sid = PCI_DEVID(info->bus, info->devfn);
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if (info->ats_enabled) {
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sdev->dev_iotlb = 1;
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sdev->qdep = info->ats_qdep;
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if (sdev->qdep >= QI_DEV_EIOTLB_MAX_INVS)
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sdev->qdep = 0;
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}
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/* Finish the setup now we know we're keeping it */
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sdev->users = 1;
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sdev->ops = ops;
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init_rcu_head(&sdev->rcu);
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if (!svm) {
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svm = kzalloc(sizeof(*svm), GFP_KERNEL);
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if (!svm) {
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ret = -ENOMEM;
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kfree(sdev);
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goto out;
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}
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svm->iommu = iommu;
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if (pasid_max > intel_pasid_max_id)
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pasid_max = intel_pasid_max_id;
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/* Do not use PASID 0, reserved for RID to PASID */
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svm->pasid = ioasid_alloc(NULL, PASID_MIN,
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pasid_max - 1, svm);
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if (svm->pasid == INVALID_IOASID) {
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kfree(svm);
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kfree(sdev);
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ret = -ENOSPC;
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goto out;
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}
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svm->notifier.ops = &intel_mmuops;
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svm->mm = mm;
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svm->flags = flags;
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INIT_LIST_HEAD_RCU(&svm->devs);
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INIT_LIST_HEAD(&svm->list);
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ret = -ENOMEM;
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if (mm) {
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ret = mmu_notifier_register(&svm->notifier, mm);
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if (ret) {
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ioasid_free(svm->pasid);
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kfree(svm);
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kfree(sdev);
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goto out;
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}
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}
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spin_lock(&iommu->lock);
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ret = intel_pasid_setup_first_level(iommu, dev,
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mm ? mm->pgd : init_mm.pgd,
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svm->pasid, FLPT_DEFAULT_DID,
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(mm ? 0 : PASID_FLAG_SUPERVISOR_MODE) |
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(cpu_feature_enabled(X86_FEATURE_LA57) ?
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PASID_FLAG_FL5LP : 0));
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spin_unlock(&iommu->lock);
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if (ret) {
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if (mm)
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mmu_notifier_unregister(&svm->notifier, mm);
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ioasid_free(svm->pasid);
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kfree(svm);
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kfree(sdev);
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goto out;
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}
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list_add_tail(&svm->list, &global_svm_list);
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} else {
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/*
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* Binding a new device with existing PASID, need to setup
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* the PASID entry.
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*/
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spin_lock(&iommu->lock);
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ret = intel_pasid_setup_first_level(iommu, dev,
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mm ? mm->pgd : init_mm.pgd,
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svm->pasid, FLPT_DEFAULT_DID,
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(mm ? 0 : PASID_FLAG_SUPERVISOR_MODE) |
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(cpu_feature_enabled(X86_FEATURE_LA57) ?
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PASID_FLAG_FL5LP : 0));
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spin_unlock(&iommu->lock);
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if (ret) {
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kfree(sdev);
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goto out;
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}
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}
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list_add_rcu(&sdev->list, &svm->devs);
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success:
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*pasid = svm->pasid;
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ret = 0;
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out:
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mutex_unlock(&pasid_mutex);
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if (mm)
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mmput(mm);
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return ret;
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}
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EXPORT_SYMBOL_GPL(intel_svm_bind_mm);
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int intel_svm_unbind_mm(struct device *dev, int pasid)
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{
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struct intel_svm_dev *sdev;
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struct intel_iommu *iommu;
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struct intel_svm *svm;
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int ret = -EINVAL;
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mutex_lock(&pasid_mutex);
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iommu = intel_svm_device_to_iommu(dev);
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if (!iommu)
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goto out;
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svm = ioasid_find(NULL, pasid, NULL);
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if (!svm)
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goto out;
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if (IS_ERR(svm)) {
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ret = PTR_ERR(svm);
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goto out;
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}
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for_each_svm_dev(sdev, svm, dev) {
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ret = 0;
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sdev->users--;
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if (!sdev->users) {
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list_del_rcu(&sdev->list);
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/* Flush the PASID cache and IOTLB for this device.
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* Note that we do depend on the hardware *not* using
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* the PASID any more. Just as we depend on other
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* devices never using PASIDs that they have no right
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* to use. We have a *shared* PASID table, because it's
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* large and has to be physically contiguous. So it's
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* hard to be as defensive as we might like. */
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intel_pasid_tear_down_entry(iommu, dev, svm->pasid);
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intel_flush_svm_range_dev(svm, sdev, 0, -1, 0);
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kfree_rcu(sdev, rcu);
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if (list_empty(&svm->devs)) {
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ioasid_free(svm->pasid);
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if (svm->mm)
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mmu_notifier_unregister(&svm->notifier, svm->mm);
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list_del(&svm->list);
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/* We mandate that no page faults may be outstanding
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* for the PASID when intel_svm_unbind_mm() is called.
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* If that is not obeyed, subtle errors will happen.
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* Let's make them less subtle... */
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memset(svm, 0x6b, sizeof(*svm));
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kfree(svm);
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}
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}
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break;
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}
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out:
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mutex_unlock(&pasid_mutex);
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return ret;
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}
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EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
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int intel_svm_is_pasid_valid(struct device *dev, int pasid)
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{
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struct intel_iommu *iommu;
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struct intel_svm *svm;
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int ret = -EINVAL;
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mutex_lock(&pasid_mutex);
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iommu = intel_svm_device_to_iommu(dev);
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if (!iommu)
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goto out;
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svm = ioasid_find(NULL, pasid, NULL);
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if (!svm)
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goto out;
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if (IS_ERR(svm)) {
|
|
ret = PTR_ERR(svm);
|
|
goto out;
|
|
}
|
|
/* init_mm is used in this case */
|
|
if (!svm->mm)
|
|
ret = 1;
|
|
else if (atomic_read(&svm->mm->mm_users) > 0)
|
|
ret = 1;
|
|
else
|
|
ret = 0;
|
|
|
|
out:
|
|
mutex_unlock(&pasid_mutex);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(intel_svm_is_pasid_valid);
|
|
|
|
/* Page request queue descriptor */
|
|
struct page_req_dsc {
|
|
union {
|
|
struct {
|
|
u64 type:8;
|
|
u64 pasid_present:1;
|
|
u64 priv_data_present:1;
|
|
u64 rsvd:6;
|
|
u64 rid:16;
|
|
u64 pasid:20;
|
|
u64 exe_req:1;
|
|
u64 pm_req:1;
|
|
u64 rsvd2:10;
|
|
};
|
|
u64 qw_0;
|
|
};
|
|
union {
|
|
struct {
|
|
u64 rd_req:1;
|
|
u64 wr_req:1;
|
|
u64 lpig:1;
|
|
u64 prg_index:9;
|
|
u64 addr:52;
|
|
};
|
|
u64 qw_1;
|
|
};
|
|
u64 priv_data[2];
|
|
};
|
|
|
|
#define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x20)
|
|
|
|
static bool access_error(struct vm_area_struct *vma, struct page_req_dsc *req)
|
|
{
|
|
unsigned long requested = 0;
|
|
|
|
if (req->exe_req)
|
|
requested |= VM_EXEC;
|
|
|
|
if (req->rd_req)
|
|
requested |= VM_READ;
|
|
|
|
if (req->wr_req)
|
|
requested |= VM_WRITE;
|
|
|
|
return (requested & ~vma->vm_flags) != 0;
|
|
}
|
|
|
|
static bool is_canonical_address(u64 addr)
|
|
{
|
|
int shift = 64 - (__VIRTUAL_MASK_SHIFT + 1);
|
|
long saddr = (long) addr;
|
|
|
|
return (((saddr << shift) >> shift) == saddr);
|
|
}
|
|
|
|
static irqreturn_t prq_event_thread(int irq, void *d)
|
|
{
|
|
struct intel_iommu *iommu = d;
|
|
struct intel_svm *svm = NULL;
|
|
int head, tail, handled = 0;
|
|
|
|
/* Clear PPR bit before reading head/tail registers, to
|
|
* ensure that we get a new interrupt if needed. */
|
|
writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
|
|
|
|
tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
|
|
head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
|
|
while (head != tail) {
|
|
struct intel_svm_dev *sdev;
|
|
struct vm_area_struct *vma;
|
|
struct page_req_dsc *req;
|
|
struct qi_desc resp;
|
|
int result;
|
|
vm_fault_t ret;
|
|
u64 address;
|
|
|
|
handled = 1;
|
|
|
|
req = &iommu->prq[head / sizeof(*req)];
|
|
|
|
result = QI_RESP_FAILURE;
|
|
address = (u64)req->addr << VTD_PAGE_SHIFT;
|
|
if (!req->pasid_present) {
|
|
pr_err("%s: Page request without PASID: %08llx %08llx\n",
|
|
iommu->name, ((unsigned long long *)req)[0],
|
|
((unsigned long long *)req)[1]);
|
|
goto no_pasid;
|
|
}
|
|
|
|
if (!svm || svm->pasid != req->pasid) {
|
|
rcu_read_lock();
|
|
svm = ioasid_find(NULL, req->pasid, NULL);
|
|
/* It *can't* go away, because the driver is not permitted
|
|
* to unbind the mm while any page faults are outstanding.
|
|
* So we only need RCU to protect the internal idr code. */
|
|
rcu_read_unlock();
|
|
if (IS_ERR_OR_NULL(svm)) {
|
|
pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n",
|
|
iommu->name, req->pasid, ((unsigned long long *)req)[0],
|
|
((unsigned long long *)req)[1]);
|
|
goto no_pasid;
|
|
}
|
|
}
|
|
|
|
result = QI_RESP_INVALID;
|
|
/* Since we're using init_mm.pgd directly, we should never take
|
|
* any faults on kernel addresses. */
|
|
if (!svm->mm)
|
|
goto bad_req;
|
|
|
|
/* If address is not canonical, return invalid response */
|
|
if (!is_canonical_address(address))
|
|
goto bad_req;
|
|
|
|
/* If the mm is already defunct, don't handle faults. */
|
|
if (!mmget_not_zero(svm->mm))
|
|
goto bad_req;
|
|
|
|
down_read(&svm->mm->mmap_sem);
|
|
vma = find_extend_vma(svm->mm, address);
|
|
if (!vma || address < vma->vm_start)
|
|
goto invalid;
|
|
|
|
if (access_error(vma, req))
|
|
goto invalid;
|
|
|
|
ret = handle_mm_fault(vma, address,
|
|
req->wr_req ? FAULT_FLAG_WRITE : 0);
|
|
if (ret & VM_FAULT_ERROR)
|
|
goto invalid;
|
|
|
|
result = QI_RESP_SUCCESS;
|
|
invalid:
|
|
up_read(&svm->mm->mmap_sem);
|
|
mmput(svm->mm);
|
|
bad_req:
|
|
/* Accounting for major/minor faults? */
|
|
rcu_read_lock();
|
|
list_for_each_entry_rcu(sdev, &svm->devs, list) {
|
|
if (sdev->sid == req->rid)
|
|
break;
|
|
}
|
|
/* Other devices can go away, but the drivers are not permitted
|
|
* to unbind while any page faults might be in flight. So it's
|
|
* OK to drop the 'lock' here now we have it. */
|
|
rcu_read_unlock();
|
|
|
|
if (WARN_ON(&sdev->list == &svm->devs))
|
|
sdev = NULL;
|
|
|
|
if (sdev && sdev->ops && sdev->ops->fault_cb) {
|
|
int rwxp = (req->rd_req << 3) | (req->wr_req << 2) |
|
|
(req->exe_req << 1) | (req->pm_req);
|
|
sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr,
|
|
req->priv_data, rwxp, result);
|
|
}
|
|
/* We get here in the error case where the PASID lookup failed,
|
|
and these can be NULL. Do not use them below this point! */
|
|
sdev = NULL;
|
|
svm = NULL;
|
|
no_pasid:
|
|
if (req->lpig || req->priv_data_present) {
|
|
/*
|
|
* Per VT-d spec. v3.0 ch7.7, system software must
|
|
* respond with page group response if private data
|
|
* is present (PDP) or last page in group (LPIG) bit
|
|
* is set. This is an additional VT-d feature beyond
|
|
* PCI ATS spec.
|
|
*/
|
|
resp.qw0 = QI_PGRP_PASID(req->pasid) |
|
|
QI_PGRP_DID(req->rid) |
|
|
QI_PGRP_PASID_P(req->pasid_present) |
|
|
QI_PGRP_PDP(req->pasid_present) |
|
|
QI_PGRP_RESP_CODE(result) |
|
|
QI_PGRP_RESP_TYPE;
|
|
resp.qw1 = QI_PGRP_IDX(req->prg_index) |
|
|
QI_PGRP_LPIG(req->lpig);
|
|
|
|
if (req->priv_data_present)
|
|
memcpy(&resp.qw2, req->priv_data,
|
|
sizeof(req->priv_data));
|
|
resp.qw2 = 0;
|
|
resp.qw3 = 0;
|
|
qi_submit_sync(&resp, iommu);
|
|
}
|
|
head = (head + sizeof(*req)) & PRQ_RING_MASK;
|
|
}
|
|
|
|
dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
|
|
|
|
return IRQ_RETVAL(handled);
|
|
}
|