mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 04:45:12 +07:00
843a85ced9
* pci/host-designware: PCI: designware: Remove unnecessary use of 'conf_lock' spinlock PCI: designware: Use new OF interrupt mapping when possible PCI: designware: Fix iATU programming for cfg1, io and mem viewport PCI: designware: Fix comment for setting number of lanes * pci/host-imx6: PCI: designware: Split Exynos and i.MX bindings * pci/host-mvebu: PCI: mvebu: Use '%pa' for printing 'phys_addr_t' type PCI: mvebu: Remove unnecessary use of 'conf_lock' spinlock PCI: mvebu: split PCIe BARs into multiple MBus windows when needed bus: mvebu-mbus: allow several windows with the same target/attribute bus: mvebu-mbus: Avoid setting an undefined window size PCI: mvebu: fix off-by-one in the computed size of the mbus windows * pci/host-tegra: PCI: tegra: Use new OF interrupt mapping when possible
77 lines
2.1 KiB
C
77 lines
2.1 KiB
C
/*
|
|
* Synopsys Designware PCIe host controller driver
|
|
*
|
|
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
|
|
* http://www.samsung.com
|
|
*
|
|
* Author: Jingoo Han <jg1.han@samsung.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#ifndef _PCIE_DESIGNWARE_H
|
|
#define _PCIE_DESIGNWARE_H
|
|
|
|
struct pcie_port_info {
|
|
u32 cfg0_size;
|
|
u32 cfg1_size;
|
|
u32 io_size;
|
|
u32 mem_size;
|
|
phys_addr_t io_bus_addr;
|
|
phys_addr_t mem_bus_addr;
|
|
};
|
|
|
|
/*
|
|
* Maximum number of MSI IRQs can be 256 per controller. But keep
|
|
* it 32 as of now. Probably we will never need more than 32. If needed,
|
|
* then increment it in multiple of 32.
|
|
*/
|
|
#define MAX_MSI_IRQS 32
|
|
#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
|
|
|
|
struct pcie_port {
|
|
struct device *dev;
|
|
u8 root_bus_nr;
|
|
void __iomem *dbi_base;
|
|
u64 cfg0_base;
|
|
void __iomem *va_cfg0_base;
|
|
u64 cfg1_base;
|
|
void __iomem *va_cfg1_base;
|
|
u64 io_base;
|
|
u64 mem_base;
|
|
struct resource cfg;
|
|
struct resource io;
|
|
struct resource mem;
|
|
struct pcie_port_info config;
|
|
int irq;
|
|
u32 lanes;
|
|
struct pcie_host_ops *ops;
|
|
int msi_irq;
|
|
struct irq_domain *irq_domain;
|
|
unsigned long msi_data;
|
|
DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
|
|
};
|
|
|
|
struct pcie_host_ops {
|
|
void (*readl_rc)(struct pcie_port *pp,
|
|
void __iomem *dbi_base, u32 *val);
|
|
void (*writel_rc)(struct pcie_port *pp,
|
|
u32 val, void __iomem *dbi_base);
|
|
int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
|
|
int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
|
|
int (*link_up)(struct pcie_port *pp);
|
|
void (*host_init)(struct pcie_port *pp);
|
|
};
|
|
|
|
int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
|
|
int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
|
|
irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
|
|
void dw_pcie_msi_init(struct pcie_port *pp);
|
|
int dw_pcie_link_up(struct pcie_port *pp);
|
|
void dw_pcie_setup_rc(struct pcie_port *pp);
|
|
int dw_pcie_host_init(struct pcie_port *pp);
|
|
|
|
#endif /* _PCIE_DESIGNWARE_H */
|