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Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
74 lines
1.7 KiB
C
74 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* arch/arm/mach-ixp4xx/nas100d-pci.c
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*
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* NAS 100d board-level PCI initialization
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*
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* based on ixdp425-pci.c:
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* Copyright (C) 2002 Intel Corporation.
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* Copyright (C) 2003-2004 MontaVista Software, Inc.
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*
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* Maintainer: http://www.nslu2-linux.org/
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*/
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <asm/mach/pci.h>
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#include <asm/mach-types.h>
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#include "irqs.h"
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#define MAX_DEV 3
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#define IRQ_LINES 3
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/* PCI controller GPIO to IRQ pin mappings */
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#define INTA 11
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#define INTB 10
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#define INTC 9
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#define INTD 8
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#define INTE 7
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void __init nas100d_pci_preinit(void)
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{
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irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
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irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
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irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
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irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
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irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
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ixp4xx_pci_preinit();
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}
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static int __init nas100d_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
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{ IXP4XX_GPIO_IRQ(INTA), -1, -1 },
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{ IXP4XX_GPIO_IRQ(INTB), -1, -1 },
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{ IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD),
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IXP4XX_GPIO_IRQ(INTE) },
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};
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if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
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return pci_irq_table[slot - 1][pin - 1];
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return -1;
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}
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struct hw_pci __initdata nas100d_pci = {
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.nr_controllers = 1,
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.ops = &ixp4xx_ops,
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.preinit = nas100d_pci_preinit,
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.setup = ixp4xx_setup,
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.map_irq = nas100d_map_irq,
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};
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int __init nas100d_pci_init(void)
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{
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if (machine_is_nas100d())
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pci_common_init(&nas100d_pci);
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return 0;
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}
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subsys_initcall(nas100d_pci_init);
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