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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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acf993a0f2
Recent changes to the Atheros at803x driver cause the approach taken here to stop working because commit6d4cd041f0("net: phy: at803x: disable delay only for RGMII mode") and commitcd28d1d6e5("net: phy: at803x: Disable phy delay for RGMII mode") fix the AR8031 driver to configure the phy's (RX/TX) delays as per the 'phy-mode' in the device tree. In particular, the phy tx (and rx) delays are updated again as per the 'phy-mode' *after* the code in here runs. Things worked before above commits, because the AR8031 comes out of reset with RX delay enabled, and the at803x driver didn't touch the delay configuration at all when "rgmii" mode was selected. It appears the code in here tries to make device trees work that incorrectly specify "rgmii", but that can't work any more and it is imperative since above commits to have the phy-mode configured correctly in the device tree. I suspect there are a few imx7d based boards using the ar8031 phy and phy-mode = "rgmii", but given I don't know which ones exactly, I am not in a position to update the respective device trees. Hence this patch is simply removing the superfluous code from the imx7d initialisation. An alternative could be to add a warning instead, but that would penalize all boards that have been updated already. Signed-off-by: André Draszik <git@andred.net> CC: Russell King <linux@armlinux.org.uk> CC: Shawn Guo <shawnguo@kernel.org> CC: Sascha Hauer <s.hauer@pengutronix.de> CC: Pengutronix Kernel Team <kernel@pengutronix.de> CC: Fabio Estevam <festevam@gmail.com> CC: NXP Linux Team <linux-imx@nxp.com> CC: Kate Stewart <kstewart@linuxfoundation.org> CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org> CC: Thomas Gleixner <tglx@linutronix.de> CC: Leonard Crestez <leonard.crestez@nxp.com> CC: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
116 lines
2.5 KiB
C
116 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*/
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#include <linux/irqchip.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
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#include <linux/of_platform.h>
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#include <linux/phy.h>
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#include <linux/regmap.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "common.h"
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static int ar8031_phy_fixup(struct phy_device *dev)
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{
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u16 val;
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/* Set RGMII IO voltage to 1.8V */
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phy_write(dev, 0x1d, 0x1f);
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phy_write(dev, 0x1e, 0x8);
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/* disable phy AR8031 SmartEEE function. */
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phy_write(dev, 0xd, 0x3);
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phy_write(dev, 0xe, 0x805d);
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phy_write(dev, 0xd, 0x4003);
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val = phy_read(dev, 0xe);
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val &= ~(0x1 << 8);
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phy_write(dev, 0xe, val);
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return 0;
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}
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static int bcm54220_phy_fixup(struct phy_device *dev)
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{
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/* enable RXC skew select RGMII copper mode */
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phy_write(dev, 0x1e, 0x21);
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phy_write(dev, 0x1f, 0x7ea8);
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phy_write(dev, 0x1e, 0x2f);
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phy_write(dev, 0x1f, 0x71b7);
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return 0;
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}
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#define PHY_ID_AR8031 0x004dd074
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#define PHY_ID_BCM54220 0x600d8589
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static void __init imx7d_enet_phy_init(void)
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{
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if (IS_BUILTIN(CONFIG_PHYLIB)) {
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phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
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ar8031_phy_fixup);
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phy_register_fixup_for_uid(PHY_ID_BCM54220, 0xffffffff,
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bcm54220_phy_fixup);
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}
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}
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static void __init imx7d_enet_clk_sel(void)
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{
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struct regmap *gpr;
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gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr");
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if (!IS_ERR(gpr)) {
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regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0);
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regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0);
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} else {
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pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n");
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}
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}
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static inline void imx7d_enet_init(void)
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{
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imx7d_enet_phy_init();
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imx7d_enet_clk_sel();
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}
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static void __init imx7d_init_machine(void)
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{
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struct device *parent;
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parent = imx_soc_device_init();
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if (parent == NULL)
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pr_warn("failed to initialize soc device\n");
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imx_anatop_init();
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imx7d_enet_init();
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}
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static void __init imx7d_init_late(void)
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{
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if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT))
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platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0);
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}
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static void __init imx7d_init_irq(void)
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{
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imx_init_revision_from_anatop();
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imx_src_init();
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irqchip_init();
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}
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static const char *const imx7d_dt_compat[] __initconst = {
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"fsl,imx7d",
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"fsl,imx7s",
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NULL,
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};
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DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)")
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.init_irq = imx7d_init_irq,
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.init_machine = imx7d_init_machine,
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.init_late = imx7d_init_late,
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.dt_compat = imx7d_dt_compat,
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MACHINE_END
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