Javi Merino 4272f98a1a ARM: 7164/3: PL330: Fix the size of the dst_cache_ctrl field ... dst_cache_ctrl affects bits 3, 1 and 0 of AWCACHE but it is a 3-bit field in the Channel Control Register (see Table 3-21 of the DMA-330 Technical Reference Manual) and should be programmed as such. Reference: <1320244259-10496-3-git-send-email-javi.merino@arm.com> Signed-off-by: Javi Merino <javi.merino@arm.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>		2012-02-15 21:10:49 +00:00
..
asm	ARM: 7164/3: PL330: Fix the size of the dst_cache_ctrl field	2012-02-15 21:10:49 +00:00