mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 19:13:15 +07:00
43c95d3694
cycle: Core changes: - Device links can optionally be added between a pin control producer and its consumers. This will affect how the system power management is handled: a pin controller will not suspend before all of its consumers have been suspended. This was necessary for the ST Microelectronics STMFX expander and need to be tested on other systems as well: it makes sense to make this default in the long run. Right now it is opt-in per driver. - Drive strength can be specified in microamps. With decreases in silicon technology, milliamps isn't granular enough, let's make it possible to select drive strengths in microamps. Right now the Meson (AMlogic) driver needs this. New drivers: - New subdriver for the Tegra 194 SoC. - New subdriver for the Qualcomm SDM845. - New subdriver for the Qualcomm SM8150. - New subdriver for the Freescale i.MX8MN (Freescale is now a product line of NXP). - New subdriver for Marvell MV98DX1135. Driver improvements: - The Bitmain BM1880 driver now supports pin config in addition to muxing. - The Qualcomm drivers can now reserve some GPIOs as taken aside and not usable for users. This is used in ACPI systems to take out some GPIO lines used by the BIOS so that noone else (neither kernel nor userspace) will play with them by mistake and crash the machine. - A slew of refurbishing around the Aspeed drivers (board management controllers for servers) in preparation for the new Aspeed AST2600 SoC. - A slew of improvements over the SH PFC drivers as usual. - Misc cleanups and fixes. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAl0oTPcACgkQQRCzN7AZ XXNTsw//aNPfkJS8gRszv58G56lyuO8h6Cq4m5eDpzhlpjx5qjELgi9h2UNGINqD 7CWxo35ufbKe0fDIcqpXmtuDMtSu6MuKT3SMepuw9uf9wxyndK4RIuyb0lpAJrx2 +NMPxzS+ARlrMmcfvXPRyPWHqAkXsQk6zcCgiuNCPtROkOZgs1YZ3+pemZw2/FMq gSLTO/95p0TPWr6YAlpByqfsA1A/onEm9HOiU2INV7DrAfUj7mnkuC1nZ4IJDFcv Gn6qQVQPah+MBzkwt4WXy5kDRozCIbg7x+FQBw3KAO23TrLDTFuNsYIWGFcP2CN2 eT8iSP3cWrXNUuEgcPD59aO07rhFooT+QBQFt2ih1dJCV1u/795wb57nxSh1YDcO M2tG+AW2EZky65FXwhLW2rq3LvmTM4kiEz3mA/DrcOAKvvQllK+6FKEhNy0StstP yvvlqoXdgH3sfOnWTAyHr35qA/pMuGEXSryWTJPqpflCvZ3wxNk+IV5nyPAtfaFz CK7U0Ya7NaEp/5ZlpE720apJ4uSqmRrLwk5Y1eKQvT46mGOk3rC9ZPIMXc8mB10/ mJ9mTubi1t4uIPnBl/T1T7f8QhNtr9hOY6wjLf1LoMeJ1XVNBqA+2uydOlBJ1iop RQ7y/Jl1SZ/gBzKCmvjPHT2+0Oui9oXGd9bQi0xQKO5Lus/nAIg= =Wdw1 -----END PGP SIGNATURE----- Merge tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.3 kernel cycle: Core changes: - Device links can optionally be added between a pin control producer and its consumers. This will affect how the system power management is handled: a pin controller will not suspend before all of its consumers have been suspended. This was necessary for the ST Microelectronics STMFX expander and need to be tested on other systems as well: it makes sense to make this default in the long run. Right now it is opt-in per driver. - Drive strength can be specified in microamps. With decreases in silicon technology, milliamps isn't granular enough, let's make it possible to select drive strengths in microamps. Right now the Meson (AMlogic) driver needs this. New drivers: - New subdriver for the Tegra 194 SoC. - New subdriver for the Qualcomm SDM845. - New subdriver for the Qualcomm SM8150. - New subdriver for the Freescale i.MX8MN (Freescale is now a product line of NXP). - New subdriver for Marvell MV98DX1135. Driver improvements: - The Bitmain BM1880 driver now supports pin config in addition to muxing. - The Qualcomm drivers can now reserve some GPIOs as taken aside and not usable for users. This is used in ACPI systems to take out some GPIO lines used by the BIOS so that noone else (neither kernel nor userspace) will play with them by mistake and crash the machine. - A slew of refurbishing around the Aspeed drivers (board management controllers for servers) in preparation for the new Aspeed AST2600 SoC. - A slew of improvements over the SH PFC drivers as usual. - Misc cleanups and fixes" * tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (106 commits) pinctrl: aspeed: Strip moved macros and structs from private header pinctrl: aspeed: Fix missed include pinctrl: baytrail: Use GENMASK() consistently pinctrl: baytrail: Re-use data structures from pinctrl-intel.h pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux() pinctrl: qcom: Add SM8150 pinctrl driver dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding dt-bindings: pinctrl: qcom: Document missing gpio nodes pinctrl: aspeed: Add implementation-related documentation pinctrl: aspeed: Split out pinmux from general pinctrl pinctrl: aspeed: Clarify comment about strapping W1C pinctrl: aspeed: Correct comment that is no longer true MAINTAINERS: Add entry for ASPEED pinctrl drivers dt-bindings: pinctrl: aspeed: Convert AST2500 bindings to json-schema dt-bindings: pinctrl: aspeed: Convert AST2400 bindings to json-schema dt-bindings: pinctrl: aspeed: Split bindings document in two pinctrl: qcom: Add irq_enable callback for msm gpio pinctrl: madera: Fixup SPDX headers pinctrl: qcom: sdm845: Fix CONFIG preprocessor guard pinctrl: tegra: Add bitmask support for parked bits ...
606 lines
13 KiB
C
606 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2016 IBM Corp.
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*/
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#include <linux/mfd/syscon.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include "../core.h"
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#include "pinctrl-aspeed.h"
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int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
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{
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struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
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return pdata->pinmux.ngroups;
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}
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const char *aspeed_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
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unsigned int group)
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{
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struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
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return pdata->pinmux.groups[group].name;
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}
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int aspeed_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
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unsigned int group, const unsigned int **pins,
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unsigned int *npins)
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{
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struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
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*pins = &pdata->pinmux.groups[group].pins[0];
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*npins = pdata->pinmux.groups[group].npins;
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return 0;
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}
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void aspeed_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
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struct seq_file *s, unsigned int offset)
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{
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seq_printf(s, " %s", dev_name(pctldev->dev));
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}
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int aspeed_pinmux_get_fn_count(struct pinctrl_dev *pctldev)
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{
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struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
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return pdata->pinmux.nfunctions;
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}
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const char *aspeed_pinmux_get_fn_name(struct pinctrl_dev *pctldev,
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unsigned int function)
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{
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struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
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return pdata->pinmux.functions[function].name;
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}
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int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev,
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unsigned int function,
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const char * const **groups,
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unsigned int * const num_groups)
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{
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struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
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*groups = pdata->pinmux.functions[function].groups;
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*num_groups = pdata->pinmux.functions[function].ngroups;
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return 0;
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}
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static int aspeed_sig_expr_enable(const struct aspeed_pinmux_data *ctx,
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const struct aspeed_sig_expr *expr)
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{
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int ret;
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ret = aspeed_sig_expr_eval(ctx, expr, true);
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if (ret < 0)
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return ret;
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if (!ret)
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return aspeed_sig_expr_set(ctx, expr, true);
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return 0;
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}
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static int aspeed_sig_expr_disable(const struct aspeed_pinmux_data *ctx,
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const struct aspeed_sig_expr *expr)
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{
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int ret;
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ret = aspeed_sig_expr_eval(ctx, expr, true);
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if (ret < 0)
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return ret;
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if (ret)
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return aspeed_sig_expr_set(ctx, expr, false);
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return 0;
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}
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/**
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* Disable a signal on a pin by disabling all provided signal expressions.
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*
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* @ctx: The pinmux context
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* @exprs: The list of signal expressions (from a priority level on a pin)
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*
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* Return: 0 if all expressions are disabled, otherwise a negative error code
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*/
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static int aspeed_disable_sig(const struct aspeed_pinmux_data *ctx,
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const struct aspeed_sig_expr **exprs)
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{
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int ret = 0;
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if (!exprs)
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return true;
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while (*exprs && !ret) {
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ret = aspeed_sig_expr_disable(ctx, *exprs);
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exprs++;
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}
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return ret;
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}
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/**
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* Search for the signal expression needed to enable the pin's signal for the
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* requested function.
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*
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* @exprs: List of signal expressions (haystack)
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* @name: The name of the requested function (needle)
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*
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* Return: A pointer to the signal expression whose function tag matches the
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* provided name, otherwise NULL.
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*
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*/
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static const struct aspeed_sig_expr *aspeed_find_expr_by_name(
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const struct aspeed_sig_expr **exprs, const char *name)
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{
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while (*exprs) {
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if (strcmp((*exprs)->function, name) == 0)
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return *exprs;
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exprs++;
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}
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return NULL;
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}
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static char *get_defined_attribute(const struct aspeed_pin_desc *pdesc,
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const char *(*get)(
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const struct aspeed_sig_expr *))
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{
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char *found = NULL;
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size_t len = 0;
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const struct aspeed_sig_expr ***prios, **funcs, *expr;
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prios = pdesc->prios;
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while ((funcs = *prios)) {
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while ((expr = *funcs)) {
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const char *str = get(expr);
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size_t delta = strlen(str) + 2;
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char *expanded;
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expanded = krealloc(found, len + delta + 1, GFP_KERNEL);
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if (!expanded) {
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kfree(found);
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return expanded;
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}
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found = expanded;
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found[len] = '\0';
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len += delta;
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strcat(found, str);
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strcat(found, ", ");
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funcs++;
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}
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prios++;
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}
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if (len < 2) {
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kfree(found);
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return NULL;
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}
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found[len - 2] = '\0';
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return found;
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}
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static const char *aspeed_sig_expr_function(const struct aspeed_sig_expr *expr)
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{
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return expr->function;
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}
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static char *get_defined_functions(const struct aspeed_pin_desc *pdesc)
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{
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return get_defined_attribute(pdesc, aspeed_sig_expr_function);
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}
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static const char *aspeed_sig_expr_signal(const struct aspeed_sig_expr *expr)
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{
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return expr->signal;
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}
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static char *get_defined_signals(const struct aspeed_pin_desc *pdesc)
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{
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return get_defined_attribute(pdesc, aspeed_sig_expr_signal);
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}
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int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
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unsigned int group)
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{
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int i;
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int ret;
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const struct aspeed_pinctrl_data *pdata =
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pinctrl_dev_get_drvdata(pctldev);
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const struct aspeed_pin_group *pgroup = &pdata->pinmux.groups[group];
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const struct aspeed_pin_function *pfunc =
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&pdata->pinmux.functions[function];
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for (i = 0; i < pgroup->npins; i++) {
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int pin = pgroup->pins[i];
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const struct aspeed_pin_desc *pdesc = pdata->pins[pin].drv_data;
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const struct aspeed_sig_expr *expr = NULL;
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const struct aspeed_sig_expr **funcs;
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const struct aspeed_sig_expr ***prios;
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pr_debug("Muxing pin %d for %s\n", pin, pfunc->name);
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if (!pdesc)
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return -EINVAL;
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prios = pdesc->prios;
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if (!prios)
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continue;
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/* Disable functions at a higher priority than that requested */
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while ((funcs = *prios)) {
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expr = aspeed_find_expr_by_name(funcs, pfunc->name);
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if (expr)
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break;
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ret = aspeed_disable_sig(&pdata->pinmux, funcs);
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if (ret)
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return ret;
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prios++;
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}
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if (!expr) {
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char *functions = get_defined_functions(pdesc);
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char *signals = get_defined_signals(pdesc);
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pr_warn("No function %s found on pin %s (%d). Found signal(s) %s for function(s) %s\n",
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pfunc->name, pdesc->name, pin, signals,
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functions);
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kfree(signals);
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kfree(functions);
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return -ENXIO;
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}
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ret = aspeed_sig_expr_enable(&pdata->pinmux, expr);
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if (ret)
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return ret;
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}
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return 0;
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}
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static bool aspeed_expr_is_gpio(const struct aspeed_sig_expr *expr)
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{
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/*
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* The signal type is GPIO if the signal name has "GPIO" as a prefix.
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* strncmp (rather than strcmp) is used to implement the prefix
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* requirement.
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*
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* expr->signal might look like "GPIOT3" in the GPIO case.
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*/
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return strncmp(expr->signal, "GPIO", 4) == 0;
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}
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static bool aspeed_gpio_in_exprs(const struct aspeed_sig_expr **exprs)
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{
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if (!exprs)
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return false;
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while (*exprs) {
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if (aspeed_expr_is_gpio(*exprs))
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return true;
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exprs++;
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}
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return false;
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}
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int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int offset)
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{
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int ret;
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const struct aspeed_pinctrl_data *pdata =
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pinctrl_dev_get_drvdata(pctldev);
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const struct aspeed_pin_desc *pdesc = pdata->pins[offset].drv_data;
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const struct aspeed_sig_expr ***prios, **funcs, *expr;
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if (!pdesc)
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return -EINVAL;
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prios = pdesc->prios;
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if (!prios)
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return -ENXIO;
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/* Disable any functions of higher priority than GPIO */
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while ((funcs = *prios)) {
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if (aspeed_gpio_in_exprs(funcs))
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break;
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ret = aspeed_disable_sig(&pdata->pinmux, funcs);
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if (ret)
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return ret;
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prios++;
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}
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if (!funcs) {
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char *signals = get_defined_signals(pdesc);
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pr_warn("No GPIO signal type found on pin %s (%d). Found: %s\n",
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pdesc->name, offset, signals);
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kfree(signals);
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return -ENXIO;
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}
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expr = *funcs;
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/*
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* Disabling all higher-priority expressions is enough to enable the
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* lowest-priority signal type. As such it has no associated
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* expression.
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*/
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if (!expr)
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return 0;
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/*
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* If GPIO is not the lowest priority signal type, assume there is only
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* one expression defined to enable the GPIO function
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*/
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return aspeed_sig_expr_enable(&pdata->pinmux, expr);
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}
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int aspeed_pinctrl_probe(struct platform_device *pdev,
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struct pinctrl_desc *pdesc,
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struct aspeed_pinctrl_data *pdata)
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{
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struct device *parent;
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struct pinctrl_dev *pctl;
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parent = pdev->dev.parent;
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if (!parent) {
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dev_err(&pdev->dev, "No parent for syscon pincontroller\n");
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return -ENODEV;
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}
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pdata->scu = syscon_node_to_regmap(parent->of_node);
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if (IS_ERR(pdata->scu)) {
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dev_err(&pdev->dev, "No regmap for syscon pincontroller parent\n");
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return PTR_ERR(pdata->scu);
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}
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pdata->pinmux.maps[ASPEED_IP_SCU] = pdata->scu;
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pctl = pinctrl_register(pdesc, &pdev->dev, pdata);
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if (IS_ERR(pctl)) {
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dev_err(&pdev->dev, "Failed to register pinctrl\n");
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return PTR_ERR(pctl);
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}
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platform_set_drvdata(pdev, pdata);
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return 0;
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}
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static inline bool pin_in_config_range(unsigned int offset,
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const struct aspeed_pin_config *config)
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{
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return offset >= config->pins[0] && offset <= config->pins[1];
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}
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static inline const struct aspeed_pin_config *find_pinconf_config(
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const struct aspeed_pinctrl_data *pdata,
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unsigned int offset,
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enum pin_config_param param)
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{
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unsigned int i;
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for (i = 0; i < pdata->nconfigs; i++) {
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if (param == pdata->configs[i].param &&
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pin_in_config_range(offset, &pdata->configs[i]))
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return &pdata->configs[i];
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}
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return NULL;
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}
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/*
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* Aspeed pin configuration description.
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*
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* @param: pinconf configuration parameter
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* @arg: The supported argument for @param, or -1 if any value is supported
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* @val: The register value to write to configure @arg for @param
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*
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* The map is to be used in conjunction with the configuration array supplied
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* by the driver implementation.
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*/
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struct aspeed_pin_config_map {
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enum pin_config_param param;
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s32 arg;
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u32 val;
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};
|
|
|
|
enum aspeed_pin_config_map_type { MAP_TYPE_ARG, MAP_TYPE_VAL };
|
|
|
|
/* Aspeed consistently both:
|
|
*
|
|
* 1. Defines "disable bits" for internal pull-downs
|
|
* 2. Uses 8mA or 16mA drive strengths
|
|
*/
|
|
static const struct aspeed_pin_config_map pin_config_map[] = {
|
|
{ PIN_CONFIG_BIAS_PULL_DOWN, 0, 1 },
|
|
{ PIN_CONFIG_BIAS_PULL_DOWN, -1, 0 },
|
|
{ PIN_CONFIG_BIAS_DISABLE, -1, 1 },
|
|
{ PIN_CONFIG_DRIVE_STRENGTH, 8, 0 },
|
|
{ PIN_CONFIG_DRIVE_STRENGTH, 16, 1 },
|
|
};
|
|
|
|
static const struct aspeed_pin_config_map *find_pinconf_map(
|
|
enum pin_config_param param,
|
|
enum aspeed_pin_config_map_type type,
|
|
s64 value)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(pin_config_map); i++) {
|
|
const struct aspeed_pin_config_map *elem;
|
|
bool match;
|
|
|
|
elem = &pin_config_map[i];
|
|
|
|
switch (type) {
|
|
case MAP_TYPE_ARG:
|
|
match = (elem->arg == -1 || elem->arg == value);
|
|
break;
|
|
case MAP_TYPE_VAL:
|
|
match = (elem->val == value);
|
|
break;
|
|
}
|
|
|
|
if (param == elem->param && match)
|
|
return elem;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset,
|
|
unsigned long *config)
|
|
{
|
|
const enum pin_config_param param = pinconf_to_config_param(*config);
|
|
const struct aspeed_pin_config_map *pmap;
|
|
const struct aspeed_pinctrl_data *pdata;
|
|
const struct aspeed_pin_config *pconf;
|
|
unsigned int val;
|
|
int rc = 0;
|
|
u32 arg;
|
|
|
|
pdata = pinctrl_dev_get_drvdata(pctldev);
|
|
pconf = find_pinconf_config(pdata, offset, param);
|
|
if (!pconf)
|
|
return -ENOTSUPP;
|
|
|
|
rc = regmap_read(pdata->scu, pconf->reg, &val);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
pmap = find_pinconf_map(param, MAP_TYPE_VAL,
|
|
(val & BIT(pconf->bit)) >> pconf->bit);
|
|
|
|
if (!pmap)
|
|
return -EINVAL;
|
|
|
|
if (param == PIN_CONFIG_DRIVE_STRENGTH)
|
|
arg = (u32) pmap->arg;
|
|
else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
|
|
arg = !!pmap->arg;
|
|
else
|
|
arg = 1;
|
|
|
|
if (!arg)
|
|
return -EINVAL;
|
|
|
|
*config = pinconf_to_config_packed(param, arg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset,
|
|
unsigned long *configs, unsigned int num_configs)
|
|
{
|
|
const struct aspeed_pinctrl_data *pdata;
|
|
unsigned int i;
|
|
int rc = 0;
|
|
|
|
pdata = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
for (i = 0; i < num_configs; i++) {
|
|
const struct aspeed_pin_config_map *pmap;
|
|
const struct aspeed_pin_config *pconf;
|
|
enum pin_config_param param;
|
|
unsigned int val;
|
|
u32 arg;
|
|
|
|
param = pinconf_to_config_param(configs[i]);
|
|
arg = pinconf_to_config_argument(configs[i]);
|
|
|
|
pconf = find_pinconf_config(pdata, offset, param);
|
|
if (!pconf)
|
|
return -ENOTSUPP;
|
|
|
|
pmap = find_pinconf_map(param, MAP_TYPE_ARG, arg);
|
|
|
|
if (WARN_ON(!pmap))
|
|
return -EINVAL;
|
|
|
|
val = pmap->val << pconf->bit;
|
|
|
|
rc = regmap_update_bits(pdata->scu, pconf->reg,
|
|
BIT(pconf->bit), val);
|
|
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
pr_debug("%s: Set SCU%02X[%d]=%d for param %d(=%d) on pin %d\n",
|
|
__func__, pconf->reg, pconf->bit, pmap->val,
|
|
param, arg, offset);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int aspeed_pin_config_group_get(struct pinctrl_dev *pctldev,
|
|
unsigned int selector,
|
|
unsigned long *config)
|
|
{
|
|
const unsigned int *pins;
|
|
unsigned int npins;
|
|
int rc;
|
|
|
|
rc = aspeed_pinctrl_get_group_pins(pctldev, selector, &pins, &npins);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
if (!npins)
|
|
return -ENODEV;
|
|
|
|
rc = aspeed_pin_config_get(pctldev, pins[0], config);
|
|
|
|
return rc;
|
|
}
|
|
|
|
int aspeed_pin_config_group_set(struct pinctrl_dev *pctldev,
|
|
unsigned int selector,
|
|
unsigned long *configs,
|
|
unsigned int num_configs)
|
|
{
|
|
const unsigned int *pins;
|
|
unsigned int npins;
|
|
int rc;
|
|
int i;
|
|
|
|
pr_debug("%s: Fetching pins for group selector %d\n",
|
|
__func__, selector);
|
|
rc = aspeed_pinctrl_get_group_pins(pctldev, selector, &pins, &npins);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
for (i = 0; i < npins; i++) {
|
|
rc = aspeed_pin_config_set(pctldev, pins[i], configs,
|
|
num_configs);
|
|
if (rc < 0)
|
|
return rc;
|
|
}
|
|
|
|
return 0;
|
|
}
|