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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e16415313c
Currently, all imx pinctrl drivers maintain a big array of struct imx_pin_reg which hard-codes data like register offset and mux mode setting for each pin function. Every time a new imx SoC support is added, we need to add such a big mount of data. With moving to single kernel build, it's only matter of time to be blamed on memory consuming. With DTC pre-processor support in place, the patch moves all these data into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and changing the PIN_FUNC_ID parsing code a little bit. The pin id gets re-numbered based on mux register offset, or config register offset if the pin has no mux register, so that kernel can identify the pin id from register offsets provided by device tree. As a bonus point of the change, those arbitrary magic numbers standing for particular PIN_FUNC_ID in device tree sources are now replaced by macros to improve the readability of dts files. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dong Aisheng <dong.aisheng@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
127 lines
2.4 KiB
Plaintext
127 lines
2.4 KiB
Plaintext
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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#include "imx53.dtsi"
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/ {
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model = "Freescale i.MX53 Evaluation Kit";
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compatible = "fsl,imx53-evk", "fsl,imx53";
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memory {
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reg = <0x70000000 0x80000000>;
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};
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leds {
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compatible = "gpio-leds";
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green {
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label = "Heartbeat";
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gpios = <&gpio7 7 0>;
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linux,default-trigger = "heartbeat";
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};
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};
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};
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&esdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc1_1>;
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cd-gpios = <&gpio3 13 0>;
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wp-gpios = <&gpio3 14 0>;
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status = "okay";
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};
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&ecspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1_1>;
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fsl,spi-num-chipselects = <2>;
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cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
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status = "okay";
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flash: at45db321d@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
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spi-max-frequency = <25000000>;
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reg = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0x0 0x40000>;
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read-only;
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};
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partition@40000 {
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label = "Kernel";
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reg = <0x40000 0x3c0000>;
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};
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};
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};
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&esdhc3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc3_1>;
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cd-gpios = <&gpio3 11 0>;
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wp-gpios = <&gpio3 12 0>;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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hog {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX53_PAD_EIM_EB2__GPIO2_30 0x80000000
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MX53_PAD_EIM_D19__GPIO3_19 0x80000000
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MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
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MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
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MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
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MX53_PAD_EIM_DA14__GPIO3_14 0x80000000
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MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
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MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
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>;
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};
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_1>;
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status = "okay";
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2_1>;
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status = "okay";
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pmic: mc13892@08 {
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compatible = "fsl,mc13892", "fsl,mc13xxx";
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reg = <0x08>;
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};
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codec: sgtl5000@0a {
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec_1>;
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phy-mode = "rmii";
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phy-reset-gpios = <&gpio7 6 0>;
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status = "okay";
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};
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