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3a4356c0c0
When CPU1 is brought out of reset, it's MMU is not turned on yet, so it will
only be able to use physical addresses. For systems with that have the
MMU page configured for 0xC0000000, 0x80000000, or 0x40000000
"BIC 0x40000000" will work just fine, as it was just converting the
virtual address of &cpu1start_addr into a physical address, ie. 0xC0000000
became 0x80000000. So for systems where the SDRAM controller was able to do a
wrap-around access, this was working fine, as it was just dropping the MSB,
but for systems where out of bounds memory access is not allowed, this would
not allow CPU1 to correctly fetch &cpu1start_addr.
This patch fixes the secondary_trampoline code to correctly fetch the
physical address of cpu1start_addr directly. The patch will subtract the
correct PAGE_OFFSET from &cpu1start_addr. And since on this platform, the
physical memory will always start at 0x0, subtracting PAGE_OFFSET from
&cpu1start_addr will allow CPU1 to correctly fetch the value of cpu1start_addr.
While at it, change the name of cpu1start_addr to socfpga_cpu1start_addr
to avoid any future naming collisions for multiplatform image.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v4: Updated commit log to correctly lay out the usage of PAGE_OFFSET and
add comments to the same effect.
v3: Used PAGE_OFFSET to get the physical address
v2: Correctly get the physical address instead of just a BIC hack.
38 lines
1011 B
ArmAsm
38 lines
1011 B
ArmAsm
/*
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* Copyright (c) 2003 ARM Limited
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* Copyright (c) u-boot contributors
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* Copyright (c) 2012 Pavel Machek <pavel@denx.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/memory.h>
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.arch armv7-a
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ENTRY(secondary_trampoline)
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/* CPU1 will always fetch from 0x0 when it is brought out of reset.
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* Thus, we can just subtract the PAGE_OFFSET to get the physical
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* address of &cpu1start_addr. This would not work for platforms
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* where the physical memory does not start at 0x0.
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*/
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adr r0, 1f
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ldmia r0, {r1, r2}
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sub r2, r2, #PAGE_OFFSET
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ldr r3, [r2]
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ldr r4, [r3]
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bx r4
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.align
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1: .long .
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.long socfpga_cpu1start_addr
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ENTRY(secondary_trampoline_end)
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ENTRY(socfpga_secondary_startup)
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bl v7_invalidate_l1
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b secondary_startup
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ENDPROC(socfpga_secondary_startup)
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