mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b2377e032f
This patch slightly changes the macros of RREG32 and WREG32, which are used when reading or writing from registers. Instead of directly calling a function in the common code from these macros, the new code calls a function from the ASIC functions interface. This change allows us to share much more code between real ASICs and simulators, which in turn reduces the maintenance burden and the chances for forgetting to port code between the ASIC files. The patch also implements the hl_poll_timeout macro, instead of calling the generic readl_poll_timeout macro. This is required to allow use of this macro in the simulator files. As a result from this change, more functions in goya.c are shared with the simulator and therefore, should not be defined as static. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
229 lines
7.7 KiB
C
229 lines
7.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2019 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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#ifndef GOYAP_H_
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#define GOYAP_H_
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#include <uapi/misc/habanalabs.h>
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#include "habanalabs.h"
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#include "include/hl_boot_if.h"
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#include "include/goya/goya_packets.h"
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#include "include/goya/goya.h"
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#include "include/goya/goya_async_events.h"
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#include "include/goya/goya_fw_if.h"
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#define NUMBER_OF_CMPLT_QUEUES 5
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#define NUMBER_OF_EXT_HW_QUEUES 5
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#define NUMBER_OF_CPU_HW_QUEUES 1
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#define NUMBER_OF_INT_HW_QUEUES 9
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#define NUMBER_OF_HW_QUEUES (NUMBER_OF_EXT_HW_QUEUES + \
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NUMBER_OF_CPU_HW_QUEUES + \
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NUMBER_OF_INT_HW_QUEUES)
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/*
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* Number of MSIX interrupts IDS:
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* Each completion queue has 1 ID
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* The event queue has 1 ID
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*/
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#define NUMBER_OF_INTERRUPTS (NUMBER_OF_CMPLT_QUEUES + 1)
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#if (NUMBER_OF_HW_QUEUES >= HL_MAX_QUEUES)
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#error "Number of H/W queues must be smaller than HL_MAX_QUEUES"
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#endif
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#if (NUMBER_OF_INTERRUPTS > GOYA_MSIX_ENTRIES)
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#error "Number of MSIX interrupts must be smaller or equal to GOYA_MSIX_ENTRIES"
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#endif
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#define QMAN_FENCE_TIMEOUT_USEC 10000 /* 10 ms */
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#define QMAN_STOP_TIMEOUT_USEC 100000 /* 100 ms */
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#define CORESIGHT_TIMEOUT_USEC 100000 /* 100 ms */
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#define GOYA_CPU_TIMEOUT_USEC 10000000 /* 10s */
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#define TPC_ENABLED_MASK 0xFF
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#define PLL_HIGH_DEFAULT 1575000000 /* 1.575 GHz */
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#define MAX_POWER_DEFAULT 200000 /* 200W */
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#define DRAM_PHYS_DEFAULT_SIZE 0x100000000ull /* 4GB */
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/* DRAM Memory Map */
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#define CPU_FW_IMAGE_SIZE 0x10000000 /* 256MB */
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#define MMU_PAGE_TABLES_SIZE 0x0FC00000 /* 252MB */
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#define MMU_DRAM_DEFAULT_PAGE_SIZE 0x00200000 /* 2MB */
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#define MMU_CACHE_MNG_SIZE 0x00001000 /* 4KB */
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#define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE
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#define MMU_PAGE_TABLES_ADDR (CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE)
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#define MMU_DRAM_DEFAULT_PAGE_ADDR (MMU_PAGE_TABLES_ADDR + \
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MMU_PAGE_TABLES_SIZE)
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#define MMU_CACHE_MNG_ADDR (MMU_DRAM_DEFAULT_PAGE_ADDR + \
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MMU_DRAM_DEFAULT_PAGE_SIZE)
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#define DRAM_KMD_END_ADDR (MMU_CACHE_MNG_ADDR + \
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MMU_CACHE_MNG_SIZE)
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#define DRAM_BASE_ADDR_USER 0x20000000
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#if (DRAM_KMD_END_ADDR > DRAM_BASE_ADDR_USER)
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#error "KMD must reserve no more than 512MB"
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#endif
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/*
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* SRAM Memory Map for KMD
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*
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* KMD occupies KMD_SRAM_SIZE bytes from the start of SRAM. It is used for
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* MME/TPC QMANs
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*
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*/
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#define MME_QMAN_BASE_OFFSET 0x000000 /* Must be 0 */
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#define MME_QMAN_LENGTH 64
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#define TPC_QMAN_LENGTH 64
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#define TPC0_QMAN_BASE_OFFSET (MME_QMAN_BASE_OFFSET + \
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(MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
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#define TPC1_QMAN_BASE_OFFSET (TPC0_QMAN_BASE_OFFSET + \
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(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
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#define TPC2_QMAN_BASE_OFFSET (TPC1_QMAN_BASE_OFFSET + \
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(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
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#define TPC3_QMAN_BASE_OFFSET (TPC2_QMAN_BASE_OFFSET + \
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(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
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#define TPC4_QMAN_BASE_OFFSET (TPC3_QMAN_BASE_OFFSET + \
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(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
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#define TPC5_QMAN_BASE_OFFSET (TPC4_QMAN_BASE_OFFSET + \
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(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
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#define TPC6_QMAN_BASE_OFFSET (TPC5_QMAN_BASE_OFFSET + \
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(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
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#define TPC7_QMAN_BASE_OFFSET (TPC6_QMAN_BASE_OFFSET + \
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(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
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#define SRAM_KMD_RES_OFFSET (TPC7_QMAN_BASE_OFFSET + \
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(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
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#if (SRAM_KMD_RES_OFFSET >= GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START)
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#error "MME/TPC QMANs SRAM space exceeds limit"
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#endif
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#define SRAM_USER_BASE_OFFSET GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START
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/* Virtual address space */
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#define VA_HOST_SPACE_START 0x1000000000000ull /* 256TB */
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#define VA_HOST_SPACE_END 0x3FF8000000000ull /* 1PB - 1TB */
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#define VA_HOST_SPACE_SIZE (VA_HOST_SPACE_END - \
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VA_HOST_SPACE_START) /* 767TB */
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#define VA_DDR_SPACE_START 0x800000000ull /* 32GB */
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#define VA_DDR_SPACE_END 0x2000000000ull /* 128GB */
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#define VA_DDR_SPACE_SIZE (VA_DDR_SPACE_END - \
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VA_DDR_SPACE_START) /* 128GB */
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#define DMA_MAX_TRANSFER_SIZE U32_MAX
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#define HW_CAP_PLL 0x00000001
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#define HW_CAP_DDR_0 0x00000002
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#define HW_CAP_DDR_1 0x00000004
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#define HW_CAP_MME 0x00000008
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#define HW_CAP_CPU 0x00000010
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#define HW_CAP_DMA 0x00000020
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#define HW_CAP_MSIX 0x00000040
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#define HW_CAP_CPU_Q 0x00000080
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#define HW_CAP_MMU 0x00000100
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#define HW_CAP_TPC_MBIST 0x00000200
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#define HW_CAP_GOLDEN 0x00000400
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#define HW_CAP_TPC 0x00000800
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enum goya_fw_component {
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FW_COMP_UBOOT,
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FW_COMP_PREBOOT
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};
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struct goya_device {
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/* TODO: remove hw_queues_lock after moving to scheduler code */
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spinlock_t hw_queues_lock;
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u64 mme_clk;
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u64 tpc_clk;
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u64 ic_clk;
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u64 ddr_bar_cur_addr;
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u32 events_stat[GOYA_ASYNC_EVENT_ID_SIZE];
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u32 hw_cap_initialized;
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};
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void goya_get_fixed_properties(struct hl_device *hdev);
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int goya_mmu_init(struct hl_device *hdev);
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void goya_init_dma_qmans(struct hl_device *hdev);
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void goya_init_mme_qmans(struct hl_device *hdev);
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void goya_init_tpc_qmans(struct hl_device *hdev);
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int goya_init_cpu_queues(struct hl_device *hdev);
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void goya_init_security(struct hl_device *hdev);
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int goya_late_init(struct hl_device *hdev);
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void goya_late_fini(struct hl_device *hdev);
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void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi);
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void goya_flush_pq_write(struct hl_device *hdev, u64 *pq, u64 exp_val);
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void goya_update_eq_ci(struct hl_device *hdev, u32 val);
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void goya_restore_phase_topology(struct hl_device *hdev);
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int goya_context_switch(struct hl_device *hdev, u32 asid);
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int goya_debugfs_i2c_read(struct hl_device *hdev, u8 i2c_bus,
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u8 i2c_addr, u8 i2c_reg, u32 *val);
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int goya_debugfs_i2c_write(struct hl_device *hdev, u8 i2c_bus,
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u8 i2c_addr, u8 i2c_reg, u32 val);
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void goya_debugfs_led_set(struct hl_device *hdev, u8 led, u8 state);
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int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id);
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int goya_test_queues(struct hl_device *hdev);
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int goya_test_cpu_queue(struct hl_device *hdev);
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int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
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u32 timeout, long *result);
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long goya_get_temperature(struct hl_device *hdev, int sensor_index, u32 attr);
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long goya_get_voltage(struct hl_device *hdev, int sensor_index, u32 attr);
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long goya_get_current(struct hl_device *hdev, int sensor_index, u32 attr);
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long goya_get_fan_speed(struct hl_device *hdev, int sensor_index, u32 attr);
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long goya_get_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr);
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void goya_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr,
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long value);
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u64 goya_get_max_power(struct hl_device *hdev);
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void goya_set_max_power(struct hl_device *hdev, u64 value);
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void goya_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq);
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void goya_add_device_attr(struct hl_device *hdev,
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struct attribute_group *dev_attr_grp);
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int goya_armcp_info_get(struct hl_device *hdev);
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int goya_debug_coresight(struct hl_device *hdev, void *data);
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void goya_mmu_prepare(struct hl_device *hdev, u32 asid);
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int goya_mmu_clear_pgt_range(struct hl_device *hdev);
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int goya_mmu_set_dram_default_page(struct hl_device *hdev);
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int goya_suspend(struct hl_device *hdev);
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int goya_resume(struct hl_device *hdev);
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void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry);
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void *goya_get_events_stat(struct hl_device *hdev, u32 *size);
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void goya_add_end_of_cb_packets(u64 kernel_address, u32 len, u64 cq_addr,
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u32 cq_val, u32 msix_vec);
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int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser);
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void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
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dma_addr_t *dma_handle, u16 *queue_len);
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u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt);
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int goya_send_heartbeat(struct hl_device *hdev);
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void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
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dma_addr_t *dma_handle);
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void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
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void *vaddr);
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#endif /* GOYAP_H_ */
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